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MIPS: Clean up MIPS MT and CMP configuration options.
This patch accomplishes the following: * Clean up wording on all MIPS MT configuration menu items. * Simplify and neaten up options selected by MIPS_MT_SMP. * Make MIPS_MT_SMTC support as deprecated. * Make MIPS_CMP support to depend on MIPS_MT_SMP also. * Remove redundant options selected by MIPS_CMP. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6019/
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@ -1829,59 +1829,48 @@ choice
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prompt "MIPS MT options"
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prompt "MIPS MT options"
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config MIPS_MT_DISABLED
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config MIPS_MT_DISABLED
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bool "Disable multithreading support."
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bool "Disable multithreading support"
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help
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help
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Use this option if your workload can't take advantage of
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Use this option if your platform does not support the MT ASE
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MIPS hardware multithreading support. On systems that don't have
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which is hardware multithreading support. On systems without
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the option of an MT-enabled processor this option will be the only
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an MT-enabled processor, this will be the only option that is
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option in this menu.
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available in this menu.
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config MIPS_MT_SMP
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config MIPS_MT_SMP
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bool "Use 1 TC on each available VPE for SMP"
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bool "Use 1 TC on each available VPE for SMP"
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depends on SYS_SUPPORTS_MULTITHREADING
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depends on SYS_SUPPORTS_MULTITHREADING
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select CPU_MIPSR2_IRQ_EI
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select SYNC_R4K
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select MIPS_MT
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select MIPS_MT
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select SMP
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select SMP
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select SYS_SUPPORTS_SCHED_SMT if SMP
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select SYS_SUPPORTS_SMP
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select SMP_UP
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select SMP_UP
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select SYS_SUPPORTS_SMP
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select SYS_SUPPORTS_SCHED_SMT
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select MIPS_PERF_SHARED_TC_COUNTERS
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select MIPS_PERF_SHARED_TC_COUNTERS
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help
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help
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This is a kernel model which is known a VSMP but lately has been
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This is a kernel model which is known as SMVP. This is supported
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marketesed into SMVP.
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on cores with the MT ASE and uses the available VPEs to implement
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Virtual SMP uses the processor's VPEs to implement virtual
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virtual processors which supports SMP. This is equivalent to the
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processors. In currently available configuration of the 34K processor
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Intel Hyperthreading feature. For further information go to
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this allows for a dual processor. Both processors will share the same
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<http://www.imgtec.com/mips/mips-multithreading.asp>.
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primary caches; each will obtain the half of the TLB for it's own
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exclusive use. For a layman this model can be described as similar to
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what Intel calls Hyperthreading.
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For further information see http://www.linux-mips.org/wiki/34K#VSMP
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config MIPS_MT_SMTC
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config MIPS_MT_SMTC
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bool "SMTC: Use all TCs on all VPEs for SMP"
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bool "Use all TCs on all VPEs for SMP (DEPRECATED)"
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depends on CPU_MIPS32_R2
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depends on CPU_MIPS32_R2
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#depends on CPU_MIPS64_R2 # once there is hardware ...
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depends on SYS_SUPPORTS_MULTITHREADING
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depends on SYS_SUPPORTS_MULTITHREADING
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select CPU_MIPSR2_IRQ_EI
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select MIPS_MT
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select MIPS_MT
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select NR_CPUS_DEFAULT_8
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select SMP
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select SMP
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select SYS_SUPPORTS_SMP
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select SMP_UP
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select SMP_UP
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select SYS_SUPPORTS_SMP
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select NR_CPUS_DEFAULT_8
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help
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help
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This is a kernel model which is known a SMTC or lately has been
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This is a kernel model which is known as SMTC. This is
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marketesed into SMVP.
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supported on cores with the MT ASE and presents all TCs
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is presenting the available TC's of the core as processors to Linux.
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available on all VPEs to support SMP. For further
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On currently available 34K processors this means a Linux system will
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information see <http://www.linux-mips.org/wiki/34K#SMTC>.
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see up to 5 processors. The implementation of the SMTC kernel differs
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significantly from VSMP and cannot efficiently coexist in the same
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kernel binary so the choice between VSMP and SMTC is a compile time
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decision.
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For further information see http://www.linux-mips.org/wiki/34K#SMTC
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endchoice
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endchoice
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@ -1958,17 +1947,13 @@ config MIPS_VPE_APSP_API
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help
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help
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config MIPS_CMP
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config MIPS_CMP
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bool "MIPS CMP framework support"
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bool "MIPS CMP support"
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depends on SYS_SUPPORTS_MIPS_CMP
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depends on SYS_SUPPORTS_MIPS_CMP && MIPS_MT_SMP
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select SMP
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select SYNC_R4K
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select SYNC_R4K
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select SYS_SUPPORTS_SMP
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select SYS_SUPPORTS_SCHED_SMT if SMP
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select WEAK_ORDERING
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select WEAK_ORDERING
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default n
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default n
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help
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help
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This is a placeholder option for the GCMP work. It will need to
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Enable Coherency Manager processor (CMP) support.
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be handled differently...
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config SB1_PASS_1_WORKAROUNDS
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config SB1_PASS_1_WORKAROUNDS
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bool
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bool
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@ -4,7 +4,7 @@ CONFIG_CPU_MIPS32_R2=y
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CONFIG_MIPS_MT_SMP=y
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CONFIG_MIPS_MT_SMP=y
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CONFIG_SCHED_SMT=y
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CONFIG_SCHED_SMT=y
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CONFIG_MIPS_CMP=y
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CONFIG_MIPS_CMP=y
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CONFIG_NR_CPUS=8
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CONFIG_NR_CPUS=2
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CONFIG_HZ_100=y
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CONFIG_HZ_100=y
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CONFIG_LOCALVERSION="cmp"
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CONFIG_LOCALVERSION="cmp"
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CONFIG_SYSVIPC=y
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CONFIG_SYSVIPC=y
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@ -58,7 +58,6 @@ CONFIG_ATALK=m
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CONFIG_DEV_APPLETALK=m
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CONFIG_DEV_APPLETALK=m
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CONFIG_IPDDP=m
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CONFIG_IPDDP=m
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CONFIG_IPDDP_ENCAP=y
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CONFIG_IPDDP_ENCAP=y
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CONFIG_IPDDP_DECAP=y
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CONFIG_NET_SCHED=y
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CONFIG_NET_SCHED=y
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CONFIG_NET_SCH_CBQ=m
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CONFIG_NET_SCH_CBQ=m
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CONFIG_NET_SCH_HTB=m
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CONFIG_NET_SCH_HTB=m
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