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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6

Browse source 
* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6:
  [SPARC64]: Update defconfig.
  [SPARC64]: Don't double-export synchronize_irq.
  [SPARC64]: Move over to GENERIC_HARDIRQS.
  [SPARC64]: Virtualize IRQ numbers.
  [SPARC64]: Kill ino_bucket->pil
  [SPARC]: Kill __irq_itoa().
  [SPARC64]: bp->pil can never be zero
  [SPARC64]: Send all device interrupts via one PIL.
  [SPARC]: Fix iommu_flush_iotlb end address
  [SPARC]: Mark smp init functions as cpuinit
  [SPARC]: Add missing rw can_lock macros
  [SPARC]: Setup cpu_possible_map
  [SPARC]: Add topology_init()
This commit is contained in:
Linus Torvalds 2006-06-20 17:39:28 -07:00
commit be883da759
59 changed files with 608 additions and 1442 deletions
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8
arch/sparc/kernel/pcic.c
View file

@ -896,13 +896,6 @@ static inline unsigned long get_irqmask(int irq_nr)
return 1 << irq_nr;
}
static inline char *pcic_irq_itoa(unsigned int irq)
{
static char buff[16];
sprintf(buff, "%d", irq);
return buff;
}
static void pcic_disable_irq(unsigned int irq_nr)
{
unsigned long mask, flags;
@ -955,7 +948,6 @@ void __init sun4m_pci_init_IRQ(void)
BTFIXUPSET_CALL(clear_clock_irq, pcic_clear_clock_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(clear_profile_irq, pcic_clear_profile_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(load_profile_irq, pcic_load_profile_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(__irq_itoa, pcic_irq_itoa, BTFIXUPCALL_NORM);
}
int pcibios_assign_resource(struct pci_dev *pdev, int resource)

34
arch/sparc/kernel/setup.c
View file

@ -31,6 +31,7 @@
#include <linux/console.h>
#include <linux/spinlock.h>
#include <linux/root_dev.h>
#include <linux/cpu.h>
#include <asm/system.h>
#include <asm/io.h>
@ -348,6 +349,8 @@ void __init setup_arch(char **cmdline_p)
init_mm.context = (unsigned long) NO_CONTEXT;
init_task.thread.kregs = &fake_swapper_regs;
smp_setup_cpu_possible_map();
paging_init();
}
@ -389,6 +392,8 @@ console_initcall(set_preferred_console);
extern char *sparc_cpu_type;
extern char *sparc_fpu_type;
static int ncpus_probed;
static int show_cpuinfo(struct seq_file *m, void *__unused)
{
seq_printf(m,
@ -411,7 +416,7 @@ static int show_cpuinfo(struct seq_file *m, void *__unused)
romvec->pv_printrev >> 16,
romvec->pv_printrev & 0xffff,
&cputypval,
num_possible_cpus(),
ncpus_probed,
num_online_cpus()
#ifndef CONFIG_SMP
, cpu_data(0).udelay_val/(500000/HZ),
@ -471,3 +476,30 @@ void sun_do_break(void)
int serial_console = -1;
int stop_a_enabled = 1;
static int __init topology_init(void)
{
int i, ncpus, err;
/* Count the number of physically present processors in
* the machine, even on uniprocessor, so that /proc/cpuinfo
* output is consistent with 2.4.x
*/
ncpus = 0;
while (!cpu_find_by_instance(ncpus, NULL, NULL))
ncpus++;
ncpus_probed = ncpus;
err = 0;
for_each_online_cpu(i) {
struct cpu *p = kzalloc(sizeof(*p), GFP_KERNEL);
if (!p)
err = -ENOMEM;
else
register_cpu(p, i, NULL);
}
return err;
}
subsys_initcall(topology_init);

36
arch/sparc/kernel/smp.c
View file

@ -58,7 +58,7 @@ cpumask_t smp_commenced_mask = CPU_MASK_NONE;
/* Used to make bitops atomic */
unsigned char bitops_spinlock = 0;
void __init smp_store_cpu_info(int id)
void __cpuinit smp_store_cpu_info(int id)
{
int cpu_node;
@ -267,22 +267,18 @@ int setup_profiling_timer(unsigned int multiplier)
void __init smp_prepare_cpus(unsigned int max_cpus)
{
extern void smp4m_boot_cpus(void);
int i, cpuid, ncpus, extra;
int i, cpuid, extra;
BUG_ON(sparc_cpu_model != sun4m);
printk("Entering SMP Mode...\n");
ncpus = 1;
extra = 0;
for (i = 0; !cpu_find_by_instance(i, NULL, &cpuid); i++) {
if (cpuid == boot_cpu_id)
continue;
if (cpuid < NR_CPUS && ncpus++ < max_cpus)
cpu_set(cpuid, phys_cpu_present_map);
else
if (cpuid >= NR_CPUS)
extra++;
}
if (max_cpus >= NR_CPUS && extra)
/* i = number of cpus */
if (extra && max_cpus > i - extra)
printk("Warning: NR_CPUS is too low to start all cpus\n");
smp_store_cpu_info(boot_cpu_id);
@ -290,7 +286,25 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
smp4m_boot_cpus();
}
void __devinit smp_prepare_boot_cpu(void)
/* Set this up early so that things like the scheduler can init
* properly. We use the same cpu mask for both the present and
* possible cpu map.
*/
void __init smp_setup_cpu_possible_map(void)
{
int instance, mid;
instance = 0;
while (!cpu_find_by_instance(instance, NULL, &mid)) {
if (mid < NR_CPUS) {
cpu_set(mid, phys_cpu_present_map);
cpu_set(mid, cpu_present_map);
}
instance++;
}
}
void __init smp_prepare_boot_cpu(void)
{
int cpuid = hard_smp_processor_id();
@ -306,7 +320,7 @@ void __devinit smp_prepare_boot_cpu(void)
cpu_set(cpuid, phys_cpu_present_map);
}
int __devinit __cpu_up(unsigned int cpu)
int __cpuinit __cpu_up(unsigned int cpu)
{
extern int smp4m_boot_one_cpu(int);
int ret;

1
arch/sparc/kernel/sparc_ksyms.c
View file

@ -163,7 +163,6 @@ EXPORT_SYMBOL(BTFIXUP_CALL(__hard_smp_processor_id));
#endif
EXPORT_SYMBOL(BTFIXUP_CALL(enable_irq));
EXPORT_SYMBOL(BTFIXUP_CALL(disable_irq));
EXPORT_SYMBOL(BTFIXUP_CALL(__irq_itoa));
EXPORT_SYMBOL(BTFIXUP_CALL(mmu_unlockarea));
EXPORT_SYMBOL(BTFIXUP_CALL(mmu_lockarea));
EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_sgl));

3
arch/sparc/kernel/sun4c_irq.c
View file

@ -198,8 +198,6 @@ static void __init sun4c_init_timers(irqreturn_t (*counter_fn)(int, void *, stru
static void sun4c_nop(void) {}
#endif
extern char *sun4m_irq_itoa(unsigned int irq);
void __init sun4c_init_IRQ(void)
{
struct linux_prom_registers int_regs[2];
@ -238,7 +236,6 @@ void __init sun4c_init_IRQ(void)
BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(clear_profile_irq, sun4c_clear_profile_irq, BTFIXUPCALL_NOP);
BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
BTFIXUPSET_CALL(__irq_itoa, sun4m_irq_itoa, BTFIXUPCALL_NORM);
sparc_init_timers = sun4c_init_timers;
#ifdef CONFIG_SMP
BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);

12
arch/sparc/kernel/sun4d_irq.c
View file

@ -560,17 +560,6 @@ void __init sun4d_init_sbi_irq(void)
}
}
static char *sun4d_irq_itoa(unsigned int irq)
{
static char buff[16];
if (irq < (1 << 5))
sprintf(buff, "%d", irq);
else
sprintf(buff, "%d,%x", sbus_to_pil[(irq >> 2) & 7], irq);
return buff;
}
void __init sun4d_init_IRQ(void)
{
local_irq_disable();
@ -581,7 +570,6 @@ void __init sun4d_init_IRQ(void)
BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(clear_profile_irq, sun4d_clear_profile_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(__irq_itoa, sun4d_irq_itoa, BTFIXUPCALL_NORM);
sparc_init_timers = sun4d_init_timers;
#ifdef CONFIG_SMP
BTFIXUPSET_CALL(set_cpu_int, sun4d_set_cpu_int, BTFIXUPCALL_NORM);

8
arch/sparc/kernel/sun4m_irq.c
View file

@ -229,13 +229,6 @@ static void sun4m_load_profile_irq(int cpu, unsigned int limit)
sun4m_timers->cpu_timers[cpu].l14_timer_limit = limit;
}
char *sun4m_irq_itoa(unsigned int irq)
{
static char buff[16];
sprintf(buff, "%d", irq);
return buff;
}
static void __init sun4m_init_timers(irqreturn_t (*counter_fn)(int, void *, struct pt_regs *))
{
int reg_count, irq, cpu;
@ -388,7 +381,6 @@ void __init sun4m_init_IRQ(void)
BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(clear_profile_irq, sun4m_clear_profile_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(__irq_itoa, sun4m_irq_itoa, BTFIXUPCALL_NORM);
sparc_init_timers = sun4m_init_timers;
#ifdef CONFIG_SMP
BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);

9
arch/sparc/kernel/sun4m_smp.c
View file

@ -66,7 +66,7 @@ static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val)
static void smp_setup_percpu_timer(void);
extern void cpu_probe(void);
void __init smp4m_callin(void)
void __cpuinit smp4m_callin(void)
{
int cpuid = hard_smp_processor_id();
@ -112,13 +112,8 @@ void __init smp4m_callin(void)
local_irq_enable();
cpu_set(cpuid, cpu_online_map);
/* last one in gets all the interrupts (for testing) */
set_irq_udt(boot_cpu_id);
}
extern void init_IRQ(void);
extern void cpu_panic(void);
/*
* Cycle through the processors asking the PROM to start each one.
*/
@ -134,7 +129,7 @@ void __init smp4m_boot_cpus(void)
local_flush_cache_all();
}
int smp4m_boot_one_cpu(int i)
int __cpuinit smp4m_boot_one_cpu(int i)
{
extern unsigned long sun4m_cpu_startup;
unsigned long *entry = &sun4m_cpu_startup;

3
arch/sparc/mm/iommu.c
View file

@ -144,8 +144,9 @@ static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
unsigned long start;
unsigned long end;
start = (unsigned long)iopte & PAGE_MASK;
start = (unsigned long)iopte;
end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
start &= PAGE_MASK;
if (viking_mxcc_present) {
while(start < end) {
viking_mxcc_flush_page(start);

4
arch/sparc64/Kconfig
View file

@ -87,6 +87,10 @@ config SYSVIPC_COMPAT
depends on COMPAT && SYSVIPC
default y
config GENERIC_HARDIRQS
bool
default y
menu "General machine setup"
config SMP

29
arch/sparc64/defconfig
View file

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.17-rc3
# Fri May 12 12:43:49 2006
# Linux kernel version: 2.6.17
# Tue Jun 20 01:26:43 2006
#
CONFIG_SPARC=y
CONFIG_SPARC64=y
@ -87,6 +87,7 @@ CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_SYSVIPC_COMPAT=y
CONFIG_GENERIC_HARDIRQS=y
#
# General machine setup
@ -183,6 +184,8 @@ CONFIG_INET_ESP=y
CONFIG_INET_IPCOMP=y
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_TCP_CONG_ADVANCED=y
@ -198,6 +201,9 @@ CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_COMPOUND=m
CONFIG_IPV6=m
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
@ -207,7 +213,10 @@ CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
CONFIG_INET6_XFRM_MODE_TUNNEL=m
CONFIG_IPV6_TUNNEL=m
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
#
@ -260,6 +269,7 @@ CONFIG_VLAN_8021Q=m
# Network testing
#
CONFIG_NET_PKTGEN=m
CONFIG_NET_TCPPROBE=m
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
@ -562,6 +572,7 @@ CONFIG_BNX2=m
# CONFIG_CHELSIO_T1 is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
# CONFIG_MYRI10GE is not set
#
# Token Ring devices
@ -811,6 +822,7 @@ CONFIG_HWMON=y
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
CONFIG_VIDEO_V4L2=y
#
# Digital Video Broadcasting Devices
@ -1134,6 +1146,19 @@ CONFIG_USB_HIDDEV=y
#
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# Misc Linux/SPARC drivers
#

2
arch/sparc64/kernel/devices.c
View file

@ -157,7 +157,7 @@ unsigned int sun4v_vdev_device_interrupt(unsigned int dev_node)
return 0;
}
return sun4v_build_irq(sun4v_vdev_devhandle, irq, 5, 0);
return sun4v_build_irq(sun4v_vdev_devhandle, irq);
}
static const char *cpu_mid_prop(void)

13
arch/sparc64/kernel/entry.S
View file

@ -22,6 +22,7 @@
#include <asm/estate.h>
#include <asm/auxio.h>
#include <asm/sfafsr.h>
#include <asm/pil.h>
#define curptr g6
@ -431,20 +432,16 @@ do_ivec:
membar #Sync
sethi %hi(ivector_table), %g2
sllx %g3, 5, %g3
sllx %g3, 3, %g3
or %g2, %lo(ivector_table), %g2
add %g2, %g3, %g3
ldub [%g3 + 0x04], %g4 /* pil */
mov 1, %g2
sllx %g2, %g4, %g2
sllx %g4, 2, %g4
TRAP_LOAD_IRQ_WORK(%g6, %g1)
lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
lduw [%g6], %g5 /* g5 = irq_work(cpu) */
stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
wr %g2, 0x0, %set_softint
stw %g3, [%g6] /* irq_work(cpu) = bucket */
wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
retry
do_ivec_xcall:
mov 0x50, %g1

1050
arch/sparc64/kernel/irq.c
View file

File diff suppressed because it is too large Load diff

38
arch/sparc64/kernel/pci.c
View file

@ -47,12 +47,6 @@ struct pci_controller_info *pci_controller_root = NULL;
/* Each PCI controller found gets a unique index. */
int pci_num_controllers = 0;
/* At boot time the user can give the kernel a command
* line option which controls if and how PCI devices
* are reordered at PCI bus probing time.
*/
int pci_device_reorder = 0;
volatile int pci_poke_in_progress;
volatile int pci_poke_cpu = -1;
volatile int pci_poke_faulted;
@ -316,27 +310,6 @@ static void __init pci_scan_each_controller_bus(void)
p->scan_bus(p);
}
/* Reorder the pci_dev chain, so that onboard devices come first
* and then come the pluggable cards.
*/
static void __init pci_reorder_devs(void)
{
struct list_head *pci_onboard = &pci_devices;
struct list_head *walk = pci_onboard->next;
while (walk != pci_onboard) {
struct pci_dev *pdev = pci_dev_g(walk);
struct list_head *walk_next = walk->next;
if (pdev->irq && (__irq_ino(pdev->irq) & 0x20)) {
list_del(walk);
list_add(walk, pci_onboard);
}
walk = walk_next;
}
}
extern void clock_probe(void);
extern void power_init(void);
@ -348,9 +321,6 @@ static int __init pcibios_init(void)
pci_scan_each_controller_bus();
if (pci_device_reorder)
pci_reorder_devs();
isa_init();
ebus_init();
clock_probe();
@ -441,14 +411,6 @@ EXPORT_SYMBOL(pcibios_bus_to_resource);
char * __init pcibios_setup(char *str)
{
if (!strcmp(str, "onboardfirst")) {
pci_device_reorder = 1;
return NULL;
}
if (!strcmp(str, "noreorder")) {
pci_device_reorder = 0;
return NULL;
}
return str;
}

81
arch/sparc64/kernel/pci_psycho.c
View file

@ -276,82 +276,13 @@ static unsigned long __onboard_imap_off[] = {
((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
(PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
/* PCI PSYCHO INO number to Sparc PIL level. */
static unsigned char psycho_pil_table[] = {
/*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
/*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
/*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
/*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
/*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
/*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
/*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
/*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
/*0x20*/5, /* SCSI */
/*0x21*/5, /* Ethernet */
/*0x22*/8, /* Parallel Port */
/*0x23*/13, /* Audio Record */
/*0x24*/14, /* Audio Playback */
/*0x25*/15, /* PowerFail */
/*0x26*/5, /* second SCSI */
/*0x27*/11, /* Floppy */
/*0x28*/5, /* Spare Hardware */
/*0x29*/9, /* Keyboard */
/*0x2a*/5, /* Mouse */
/*0x2b*/12, /* Serial */
/*0x2c*/10, /* Timer 0 */
/*0x2d*/11, /* Timer 1 */
/*0x2e*/15, /* Uncorrectable ECC */
/*0x2f*/15, /* Correctable ECC */
/*0x30*/15, /* PCI Bus A Error */
/*0x31*/15, /* PCI Bus B Error */
/*0x32*/15, /* Power Management */
};
static int psycho_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
{
int ret;
ret = psycho_pil_table[ino];
if (ret == 0 && pdev == NULL) {
ret = 5;
} else if (ret == 0) {
switch ((pdev->class >> 16) & 0xff) {
case PCI_BASE_CLASS_STORAGE:
ret = 5;
break;
case PCI_BASE_CLASS_NETWORK:
ret = 6;
break;
case PCI_BASE_CLASS_DISPLAY:
ret = 9;
break;
case PCI_BASE_CLASS_MULTIMEDIA:
case PCI_BASE_CLASS_MEMORY:
case PCI_BASE_CLASS_BRIDGE:
case PCI_BASE_CLASS_SERIAL:
ret = 10;
break;
default:
ret = 5;
break;
};
}
return ret;
}
static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
struct pci_dev *pdev,
unsigned int ino)
{
struct ino_bucket *bucket;
unsigned long imap, iclr;
unsigned long imap_off, iclr_off;
int pil, inofixup = 0;
int inofixup = 0;
ino &= PCI_IRQ_INO;
if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
@ -367,11 +298,6 @@ static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
}
/* Now build the IRQ bucket. */
pil = psycho_ino_to_pil(pdev, ino);
if (PIL_RESERVED(pil))
BUG();
imap = pbm->controller_regs + imap_off;
imap += 4;
@ -382,10 +308,7 @@ static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
if ((ino & 0x20) == 0)
inofixup = ino & 0x03;
bucket = __bucket(build_irq(pil, inofixup, iclr, imap));
bucket->flags |= IBF_PCI;
return __irq(bucket);
return build_irq(inofixup, iclr, imap);
}
/* PSYCHO error handling support. */

99
arch/sparc64/kernel/pci_sabre.c
View file

@ -523,78 +523,6 @@ static unsigned long __onboard_imap_off[] = {
((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
(SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
/* PCI SABRE INO number to Sparc PIL level. */
static unsigned char sabre_pil_table[] = {
/*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
/*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
/*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
/*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
/*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
/*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
/*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
/*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
/*0x20*/5, /* SCSI */
/*0x21*/5, /* Ethernet */
/*0x22*/8, /* Parallel Port */
/*0x23*/13, /* Audio Record */
/*0x24*/14, /* Audio Playback */
/*0x25*/15, /* PowerFail */
/*0x26*/5, /* second SCSI */
/*0x27*/11, /* Floppy */
/*0x28*/5, /* Spare Hardware */
/*0x29*/9, /* Keyboard */
/*0x2a*/5, /* Mouse */
/*0x2b*/12, /* Serial */
/*0x2c*/10, /* Timer 0 */
/*0x2d*/11, /* Timer 1 */
/*0x2e*/15, /* Uncorrectable ECC */
/*0x2f*/15, /* Correctable ECC */
/*0x30*/15, /* PCI Bus A Error */
/*0x31*/15, /* PCI Bus B Error */
/*0x32*/15, /* Power Management */
};
static int sabre_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
{
int ret;
if (pdev &&
pdev->vendor == PCI_VENDOR_ID_SUN &&
pdev->device == PCI_DEVICE_ID_SUN_RIO_USB)
return 9;
ret = sabre_pil_table[ino];
if (ret == 0 && pdev == NULL) {
ret = 5;
} else if (ret == 0) {
switch ((pdev->class >> 16) & 0xff) {
case PCI_BASE_CLASS_STORAGE:
ret = 5;
break;
case PCI_BASE_CLASS_NETWORK:
ret = 6;
break;
case PCI_BASE_CLASS_DISPLAY:
ret = 9;
break;
case PCI_BASE_CLASS_MULTIMEDIA:
case PCI_BASE_CLASS_MEMORY:
case PCI_BASE_CLASS_BRIDGE:
case PCI_BASE_CLASS_SERIAL:
ret = 10;
break;
default:
ret = 5;
break;
};
}
return ret;
}
/* When a device lives behind a bridge deeper in the PCI bus topology
* than APB, a special sequence must run to make sure all pending DMA
* transfers at the time of IRQ delivery are visible in the coherency
@ -602,7 +530,7 @@ static int sabre_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
* side of the non-APB bridge, then perform a read of Sabre's DMA
* write-sync register.
*/
static void sabre_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_arg2)
static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
{
struct pci_dev *pdev = _arg1;
unsigned long sync_reg = (unsigned long) _arg2;
@ -616,10 +544,10 @@ static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
struct pci_dev *pdev,
unsigned int ino)
{
struct ino_bucket *bucket;
unsigned long imap, iclr;
unsigned long imap_off, iclr_off;
int pil, inofixup = 0;
int inofixup = 0;
int virt_irq;
ino &= PCI_IRQ_INO;
if (ino < SABRE_ONBOARD_IRQ_BASE) {
@ -635,11 +563,6 @@ static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
}
/* Now build the IRQ bucket. */
pil = sabre_ino_to_pil(pdev, ino);
if (PIL_RESERVED(pil))
BUG();
imap = pbm->controller_regs + imap_off;
imap += 4;
@ -650,23 +573,23 @@ static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
if ((ino & 0x20) == 0)
inofixup = ino & 0x03;
bucket = __bucket(build_irq(pil, inofixup, iclr, imap));
bucket->flags |= IBF_PCI;
virt_irq = build_irq(inofixup, iclr, imap);
if (pdev) {
struct pcidev_cookie *pcp = pdev->sysdata;
if (pdev->bus->number != pcp->pbm->pci_first_busno) {
struct pci_controller_info *p = pcp->pbm->parent;
struct irq_desc *d = bucket->irq_info;
d->pre_handler = sabre_wsync_handler;
d->pre_handler_arg1 = pdev;
d->pre_handler_arg2 = (void *)
p->pbm_A.controller_regs + SABRE_WRSYNC;
irq_install_pre_handler(virt_irq,
sabre_wsync_handler,
pdev,
(void *)
p->pbm_A.controller_regs +
SABRE_WRSYNC);
}
}
return __irq(bucket);
return virt_irq;
}
/* SABRE error handling support. */

192
arch/sparc64/kernel/pci_schizo.c
View file

@ -232,105 +232,10 @@ static unsigned long schizo_iclr_offset(unsigned long ino)
return SCHIZO_ICLR_BASE + (ino * 8UL);
}
/* PCI SCHIZO INO number to Sparc PIL level. This table only matters for
* INOs which will not have an associated PCI device struct, ie. onboard
* EBUS devices and PCI controller internal error interrupts.
*/
static unsigned char schizo_pil_table[] = {
/*0x00*/0, 0, 0, 0, /* PCI slot 0 Int A, B, C, D */
/*0x04*/0, 0, 0, 0, /* PCI slot 1 Int A, B, C, D */
/*0x08*/0, 0, 0, 0, /* PCI slot 2 Int A, B, C, D */
/*0x0c*/0, 0, 0, 0, /* PCI slot 3 Int A, B, C, D */
/*0x10*/0, 0, 0, 0, /* PCI slot 4 Int A, B, C, D */
/*0x14*/0, 0, 0, 0, /* PCI slot 5 Int A, B, C, D */
/*0x18*/5, /* SCSI */
/*0x19*/5, /* second SCSI */
/*0x1a*/0, /* UNKNOWN */
/*0x1b*/0, /* UNKNOWN */
/*0x1c*/8, /* Parallel */
/*0x1d*/5, /* Ethernet */
/*0x1e*/8, /* Firewire-1394 */
/*0x1f*/9, /* USB */
/*0x20*/13, /* Audio Record */
/*0x21*/14, /* Audio Playback */
/*0x22*/12, /* Serial */
/*0x23*/5, /* EBUS I2C */
/*0x24*/10, /* RTC Clock */
/*0x25*/11, /* Floppy */
/*0x26*/0, /* UNKNOWN */
/*0x27*/0, /* UNKNOWN */
/*0x28*/0, /* UNKNOWN */
/*0x29*/0, /* UNKNOWN */
/*0x2a*/10, /* UPA 1 */
/*0x2b*/10, /* UPA 2 */
/*0x2c*/0, /* UNKNOWN */
/*0x2d*/0, /* UNKNOWN */
/*0x2e*/0, /* UNKNOWN */
/*0x2f*/0, /* UNKNOWN */
/*0x30*/15, /* Uncorrectable ECC */
/*0x31*/15, /* Correctable ECC */
/*0x32*/15, /* PCI Bus A Error */
/*0x33*/15, /* PCI Bus B Error */
/*0x34*/15, /* Safari Bus Error */
/*0x35*/0, /* Reserved */
/*0x36*/0, /* Reserved */
/*0x37*/0, /* Reserved */
/*0x38*/0, /* Reserved for NewLink */
/*0x39*/0, /* Reserved for NewLink */
/*0x3a*/0, /* Reserved for NewLink */
/*0x3b*/0, /* Reserved for NewLink */
/*0x3c*/0, /* Reserved for NewLink */
/*0x3d*/0, /* Reserved for NewLink */
/*0x3e*/0, /* Reserved for NewLink */
/*0x3f*/0, /* Reserved for NewLink */
};
static int schizo_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
{
int ret;
if (pdev &&
pdev->vendor == PCI_VENDOR_ID_SUN &&
pdev->device == PCI_DEVICE_ID_SUN_RIO_USB)
return 9;
ret = schizo_pil_table[ino];
if (ret == 0 && pdev == NULL) {
ret = 5;
} else if (ret == 0) {
switch ((pdev->class >> 16) & 0xff) {
case PCI_BASE_CLASS_STORAGE:
ret = 5;
break;
case PCI_BASE_CLASS_NETWORK:
ret = 6;
break;
case PCI_BASE_CLASS_DISPLAY:
ret = 9;
break;
case PCI_BASE_CLASS_MULTIMEDIA:
case PCI_BASE_CLASS_MEMORY:
case PCI_BASE_CLASS_BRIDGE:
case PCI_BASE_CLASS_SERIAL:
ret = 10;
break;
default:
ret = 5;
break;
};
}
return ret;
}
static void tomatillo_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_arg2)
static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
{
unsigned long sync_reg = (unsigned long) _arg2;
u64 mask = 1UL << (__irq_ino(__irq(bucket)) & IMAP_INO);
u64 mask = 1UL << (ino & IMAP_INO);
u64 val;
int limit;
@ -365,30 +270,33 @@ static void tomatillo_wsync_handler(struct ino_bucket *bucket, void *_arg1, void
}
}
static unsigned long schizo_ino_to_iclr(struct pci_pbm_info *pbm,
unsigned int ino)
{
ino &= PCI_IRQ_INO;
return pbm->pbm_regs + schizo_iclr_offset(ino) + 4;
}
static unsigned long schizo_ino_to_imap(struct pci_pbm_info *pbm,
unsigned int ino)
{
ino &= PCI_IRQ_INO;
return pbm->pbm_regs + schizo_imap_offset(ino) + 4;
}
static unsigned int schizo_irq_build(struct pci_pbm_info *pbm,
struct pci_dev *pdev,
unsigned int ino)
{
struct ino_bucket *bucket;
unsigned long imap, iclr;
unsigned long imap_off, iclr_off;
int pil, ign_fixup;
int ign_fixup;
int virt_irq;
ino &= PCI_IRQ_INO;
imap_off = schizo_imap_offset(ino);
/* Now build the IRQ bucket. */
pil = schizo_ino_to_pil(pdev, ino);
if (PIL_RESERVED(pil))
BUG();
imap = pbm->pbm_regs + imap_off;
imap += 4;
iclr_off = schizo_iclr_offset(ino);
iclr = pbm->pbm_regs + iclr_off;
iclr += 4;
imap = schizo_ino_to_imap(pbm, ino);
iclr = schizo_ino_to_iclr(pbm, ino);
/* On Schizo, no inofixup occurs. This is because each
* INO has it's own IMAP register. On Psycho and Sabre
@ -405,19 +313,17 @@ static unsigned int schizo_irq_build(struct pci_pbm_info *pbm,
ign_fixup = (1 << 6);
}
bucket = __bucket(build_irq(pil, ign_fixup, iclr, imap));
bucket->flags |= IBF_PCI;
virt_irq = build_irq(ign_fixup, iclr, imap);
if (pdev && pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
struct irq_desc *p = bucket->irq_info;
p->pre_handler = tomatillo_wsync_handler;
p->pre_handler_arg1 = ((pbm->chip_version <= 4) ?
(void *) 1 : (void *) 0);
p->pre_handler_arg2 = (void *) pbm->sync_reg;
irq_install_pre_handler(virt_irq,
tomatillo_wsync_handler,
((pbm->chip_version <= 4) ?
(void *) 1 : (void *) 0),
(void *) pbm->sync_reg);
}
return __irq(bucket);
return virt_irq;
}
/* SCHIZO error handling support. */
@ -458,7 +364,6 @@ struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino)
static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq)
{
struct pci_pbm_info *pbm;
struct ino_bucket *bucket;
unsigned long iclr;
/* Do not clear the interrupt for the other PCI bus.
@ -476,11 +381,11 @@ static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq)
else
pbm = &p->pbm_A;
irq = schizo_irq_build(pbm, NULL,
(pbm->portid << 6) | (irq & IMAP_INO));
bucket = __bucket(irq);
iclr = bucket->iclr;
schizo_irq_build(pbm, NULL,
(pbm->portid << 6) | (irq & IMAP_INO));
iclr = schizo_ino_to_iclr(pbm,
(pbm->portid << 6) | (irq & IMAP_INO));
upa_writel(ICLR_IDLE, iclr);
}
@ -1225,7 +1130,6 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
{
struct pci_pbm_info *pbm;
unsigned int irq;
struct ino_bucket *bucket;
u64 tmp, err_mask, err_no_mask;
/* Build IRQs and register handlers. */
@ -1237,8 +1141,7 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
bucket = __bucket(irq);
tmp = upa_readl(bucket->imap);
tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO));
upa_writel(tmp, (pbm->pbm_regs +
schizo_imap_offset(SCHIZO_UE_INO) + 4));
@ -1250,8 +1153,7 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
bucket = __bucket(irq);
tmp = upa_readl(bucket->imap);
tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO));
upa_writel(tmp, (pbm->pbm_regs +
schizo_imap_offset(SCHIZO_CE_INO) + 4));
@ -1264,8 +1166,8 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
bucket = __bucket(irq);
tmp = upa_readl(bucket->imap);
tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
SCHIZO_PCIERR_A_INO)));
upa_writel(tmp, (pbm->pbm_regs +
schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
@ -1278,8 +1180,8 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
bucket = __bucket(irq);
tmp = upa_readl(bucket->imap);
tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
SCHIZO_PCIERR_B_INO)));
upa_writel(tmp, (pbm->pbm_regs +
schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
@ -1291,8 +1193,8 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
bucket = __bucket(irq);
tmp = upa_readl(bucket->imap);
tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
SCHIZO_SERR_INO)));
upa_writel(tmp, (pbm->pbm_regs +
schizo_imap_offset(SCHIZO_SERR_INO) + 4));
@ -1363,7 +1265,6 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
{
struct pci_pbm_info *pbm;
unsigned int irq;
struct ino_bucket *bucket;
u64 tmp, err_mask, err_no_mask;
/* Build IRQs and register handlers. */
@ -1375,8 +1276,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
bucket = __bucket(irq);
tmp = upa_readl(bucket->imap);
tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO));
upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_UE_INO) + 4));
pbm = pbm_for_ino(p, SCHIZO_CE_INO);
@ -1387,8 +1287,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
bucket = __bucket(irq);
tmp = upa_readl(bucket->imap);
tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO));
upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_CE_INO) + 4));
pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
@ -1399,8 +1298,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
bucket = __bucket(irq);
tmp = upa_readl(bucket->imap);
tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO));
upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
@ -1411,8 +1309,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
bucket = __bucket(irq);
tmp = upa_readl(bucket->imap);
tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO));
upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
@ -1423,8 +1320,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
pbm->name);
prom_halt();
}
bucket = __bucket(irq);
tmp = upa_readl(bucket->imap);
tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_SERR_INO));
upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_SERR_INO) + 4));
/* Enable UE and CE interrupts for controller. */

32
arch/sparc64/kernel/pci_sun4v.c
View file

@ -843,38 +843,8 @@ static unsigned int pci_sun4v_irq_build(struct pci_pbm_info *pbm,
unsigned int devino)
{
u32 devhandle = pbm->devhandle;
int pil;
pil = 5;
if (pdev) {
switch ((pdev->class >> 16) & 0xff) {
case PCI_BASE_CLASS_STORAGE:
pil = 5;
break;
case PCI_BASE_CLASS_NETWORK:
pil = 6;
break;
case PCI_BASE_CLASS_DISPLAY:
pil = 9;
break;
case PCI_BASE_CLASS_MULTIMEDIA:
case PCI_BASE_CLASS_MEMORY:
case PCI_BASE_CLASS_BRIDGE:
case PCI_BASE_CLASS_SERIAL:
pil = 10;
break;
default:
pil = 5;
break;
};
}
BUG_ON(PIL_RESERVED(pil));
return sun4v_build_irq(devhandle, devino, pil, IBF_PCI);
return sun4v_build_irq(devhandle, devino);
}
static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)

47
arch/sparc64/kernel/sbus.c
View file

@ -691,36 +691,6 @@ void sbus_set_sbus64(struct sbus_dev *sdev, int bursts)
upa_writeq(val, cfg_reg);
}
/* SBUS SYSIO INO number to Sparc PIL level. */
static unsigned char sysio_ino_to_pil[] = {
0, 5, 5, 7, 5, 7, 8, 9, /* SBUS slot 0 */
0, 5, 5, 7, 5, 7, 8, 9, /* SBUS slot 1 */
0, 5, 5, 7, 5, 7, 8, 9, /* SBUS slot 2 */
0, 5, 5, 7, 5, 7, 8, 9, /* SBUS slot 3 */
5, /* Onboard SCSI */
5, /* Onboard Ethernet */
/*XXX*/ 8, /* Onboard BPP */
0, /* Bogon */
13, /* Audio */
/*XXX*/15, /* PowerFail */
0, /* Bogon */
0, /* Bogon */
12, /* Zilog Serial Channels (incl. Keyboard/Mouse lines) */
11, /* Floppy */
0, /* Spare Hardware (bogon for now) */
0, /* Keyboard (bogon for now) */
0, /* Mouse (bogon for now) */
0, /* Serial (bogon for now) */
0, 0, /* Bogon, Bogon */
10, /* Timer 0 */
11, /* Timer 1 */
0, 0, /* Bogon, Bogon */
15, /* Uncorrectable SBUS Error */
15, /* Correctable SBUS Error */
15, /* SBUS Error */
/*XXX*/ 0, /* Power Management (bogon for now) */
};
/* INO number to IMAP register offset for SYSIO external IRQ's.
* This should conform to both Sunfire/Wildfire server and Fusion
* desktop designs.
@ -812,21 +782,12 @@ unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
struct sbus_iommu *iommu = sbus->iommu;
unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
unsigned long imap, iclr;
int pil, sbus_level = 0;
pil = sysio_ino_to_pil[ino];
if (!pil) {
printk("sbus_irq_build: Bad SYSIO INO[%x]\n", ino);
panic("Bad SYSIO IRQ translations...");
}
if (PIL_RESERVED(pil))
BUG();
int sbus_level = 0;
imap = sysio_irq_offsets[ino];
if (imap == ((unsigned long)-1)) {
prom_printf("get_irq_translations: Bad SYSIO INO[%x] cpu[%d]\n",
ino, pil);
prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
ino);
prom_halt();
}
imap += reg_base;
@ -860,7 +821,7 @@ unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
}
return build_irq(pil, sbus_level, iclr, imap);
return build_irq(sbus_level, iclr, imap);
}
/* Error interrupt handling. */

7
arch/sparc64/kernel/sparc64_ksyms.c
View file

@ -125,9 +125,6 @@ EXPORT_SYMBOL(__write_lock);
EXPORT_SYMBOL(__write_unlock);
EXPORT_SYMBOL(__write_trylock);
/* Hard IRQ locking */
EXPORT_SYMBOL(synchronize_irq);
#if defined(CONFIG_MCOUNT)
extern void _mcount(void);
EXPORT_SYMBOL(_mcount);
@ -175,10 +172,6 @@ EXPORT_SYMBOL(set_bit);
EXPORT_SYMBOL(clear_bit);
EXPORT_SYMBOL(change_bit);
EXPORT_SYMBOL(ivector_table);
EXPORT_SYMBOL(enable_irq);
EXPORT_SYMBOL(disable_irq);
EXPORT_SYMBOL(__flushw_user);
EXPORT_SYMBOL(tlb_type);

15
arch/sparc64/kernel/sun4v_ivec.S
View file

@ -5,6 +5,7 @@
#include <asm/cpudata.h>
#include <asm/intr_queue.h>
#include <asm/pil.h>
.text
.align 32
@ -102,23 +103,17 @@ sun4v_dev_mondo:
/* Get &ivector_table[IVEC] into %g4. */
sethi %hi(ivector_table), %g4
sllx %g3, 5, %g3
sllx %g3, 3, %g3
or %g4, %lo(ivector_table), %g4
add %g4, %g3, %g4
/* Load IRQ %pil into %g5. */
ldub [%g4 + 0x04], %g5
/* Insert ivector_table[] entry into __irq_work[] queue. */
sllx %g5, 2, %g3
lduw [%g1 + %g3], %g2 /* g2 = irq_work(cpu, pil) */
lduw [%g1], %g2 /* g2 = irq_work(cpu) */
stw %g2, [%g4 + 0x00] /* bucket->irq_chain = g2 */
stw %g4, [%g1 + %g3] /* irq_work(cpu, pil) = bucket */
stw %g4, [%g1] /* irq_work(cpu) = bucket */
/* Signal the interrupt by setting (1 << pil) in %softint. */
mov 1, %g2
sllx %g2, %g5, %g2
wr %g2, 0x0, %set_softint
wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
sun4v_dev_mondo_queue_empty:
retry

16
arch/sparc64/kernel/time.c
View file

@ -457,7 +457,7 @@ static inline void timer_check_rtc(void)
}
}
static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
{
unsigned long ticks, compare, pstate;
@ -1020,19 +1020,9 @@ static unsigned long sparc64_init_timers(void)
return clock;
}
static void sparc64_start_timers(irqreturn_t (*cfunc)(int, void *, struct pt_regs *))
static void sparc64_start_timers(void)
{
unsigned long pstate;
int err;
/* Register IRQ handler. */
err = request_irq(build_irq(0, 0, 0UL, 0UL), cfunc, 0,
"timer", NULL);
if (err) {
prom_printf("Serious problem, cannot register TICK_INT\n");
prom_halt();
}
/* Guarantee that the following sequences execute
* uninterrupted.
@ -1116,7 +1106,7 @@ void __init time_init(void)
/* Now that the interpolator is registered, it is
* safe to start the timer ticking.
*/
sparc64_start_timers(timer_interrupt);
sparc64_start_timers();
timer_ticks_per_nsec_quotient =
(((NSEC_PER_SEC << SPARC64_NSEC_PER_CYC_SHIFT) +

4
arch/sparc64/kernel/traps.c
View file

@ -2544,7 +2544,9 @@ void __init trap_init(void)
(TRAP_PER_CPU_TSB_HUGE !=
offsetof(struct trap_per_cpu, tsb_huge)) ||
(TRAP_PER_CPU_TSB_HUGE_TEMP !=
offsetof(struct trap_per_cpu, tsb_huge_temp)))
offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
(TRAP_PER_CPU_IRQ_WORKLIST !=
offsetof(struct trap_per_cpu, irq_worklist)))
trap_per_cpu_offsets_are_bolixed_dave();
if ((TSB_CONFIG_TSB !=

10
arch/sparc64/kernel/ttable.S
View file

@ -58,13 +58,11 @@ tl0_irq2: BTRAP(0x42)
tl0_irq3: BTRAP(0x43)
tl0_irq4: BTRAP(0x44)
#endif
tl0_irq5: TRAP_IRQ(handler_irq, 5) TRAP_IRQ(handler_irq, 6)
tl0_irq7: TRAP_IRQ(handler_irq, 7) TRAP_IRQ(handler_irq, 8)
tl0_irq9: TRAP_IRQ(handler_irq, 9) TRAP_IRQ(handler_irq, 10)
tl0_irq11: TRAP_IRQ(handler_irq, 11) TRAP_IRQ(handler_irq, 12)
tl0_irq13: TRAP_IRQ(handler_irq, 13)
tl0_irq5: TRAP_IRQ(handler_irq, 5)
tl0_irq6: BTRAP(0x46) BTRAP(0x47) BTRAP(0x48) BTRAP(0x49)
tl0_irq10: BTRAP(0x4a) BTRAP(0x4b) BTRAP(0x4c) BTRAP(0x4d)
#ifndef CONFIG_SMP
tl0_irq14: TRAP_IRQ(handler_irq, 14)
tl0_irq14: TRAP_IRQ(timer_irq, 14)
#else
tl0_irq14: TICK_SMP_IRQ
#endif

4
drivers/atm/fore200e.c
View file

@ -167,13 +167,9 @@ fore200e_atm2fore_aal(int aal)
static char*
fore200e_irq_itoa(int irq)
{
#if defined(__sparc_v9__)
return __irq_itoa(irq);
#else
static char str[8];
sprintf(str, "%d", irq);
return str;
#endif
}

4
drivers/char/rtc.c
View file

@ -960,10 +960,6 @@ static int __init rtc_init(void)
* PCI Slot 2 INTA# (and some INTx# in Slot 1).
*/
if (request_irq(rtc_irq, rtc_interrupt, SA_SHIRQ, "rtc", (void *)&rtc_port)) {
/*
* Standard way for sparc to print irq's is to use
* __irq_itoa(). I think for EBus it's ok to use %d.
*/
printk(KERN_ERR "rtc: cannot register IRQ %d\n", rtc_irq);
return -EIO;
}

2
drivers/fc4/soc.c
View file

@ -643,7 +643,7 @@ static inline void soc_init(struct sbus_dev *sdev, int no)
return;
}
SOD(("SOC uses IRQ%s\n", __irq_itoa(irq)))
SOD(("SOC uses IRQ %d\n", irq))
s->port[0].fc.irq = irq;
s->port[1].fc.irq = irq;

2
drivers/fc4/socal.c
View file

@ -767,7 +767,7 @@ static inline void socal_init(struct sbus_dev *sdev, int no)
return;
}
SOD(("SOCAL uses IRQ %s\n", __irq_itoa(irq)))
SOD(("SOCAL uses IRQ %d\n", irq))
s->port[0].fc.irq = irq;
s->port[1].fc.irq = irq;

7
drivers/ide/ide-probe.c
View file

@ -1138,16 +1138,11 @@ static int init_irq (ide_hwif_t *hwif)
spin_unlock_irq(&ide_lock);
}
#if !defined(__mc68000__) && !defined(CONFIG_APUS) && !defined(__sparc__)
#if !defined(__mc68000__) && !defined(CONFIG_APUS)
printk("%s at 0x%03lx-0x%03lx,0x%03lx on irq %d", hwif->name,
hwif->io_ports[IDE_DATA_OFFSET],
hwif->io_ports[IDE_DATA_OFFSET]+7,
hwif->io_ports[IDE_CONTROL_OFFSET], hwif->irq);
#elif defined(__sparc__)
printk("%s at 0x%03lx-0x%03lx,0x%03lx on irq %s", hwif->name,
hwif->io_ports[IDE_DATA_OFFSET],
hwif->io_ports[IDE_DATA_OFFSET]+7,
hwif->io_ports[IDE_CONTROL_OFFSET], __irq_itoa(hwif->irq));
#else
printk("%s at 0x%08lx on irq %d", hwif->name,
hwif->io_ports[IDE_DATA_OFFSET], hwif->irq);

5
drivers/ide/setup-pci.c
View file

@ -694,13 +694,8 @@ static int do_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d,
goto out;
}
if (noisy)
#ifdef __sparc__
printk(KERN_INFO "%s: 100%% native mode on irq %s\n",
d->name, __irq_itoa(pciirq));
#else
printk(KERN_INFO "%s: 100%% native mode on irq %d\n",
d->name, pciirq);
#endif
}
/* FIXME: silent failure can happen */

4
drivers/ieee1394/ohci1394.c
View file

@ -586,11 +586,7 @@ static void ohci_initialize(struct ti_ohci *ohci)
reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
buf = reg_read(ohci, OHCI1394_Version);
#ifndef __sparc__
sprintf (irq_buf, "%d", ohci->dev->irq);
#else
sprintf (irq_buf, "%s", __irq_itoa(ohci->dev->irq));
#endif
PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%s] "
"MMIO=[%lx-%lx] Max Packet=[%d] IR/IT contexts=[%d/%d]",
((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),

4
drivers/ieee1394/pcilynx.c
View file

@ -1252,11 +1252,7 @@ static int __devinit add_card(struct pci_dev *dev,
/* Fix buggy cards with autoboot pin not tied low: */
reg_write(lynx, DMA0_CHAN_CTRL, 0);
#ifndef __sparc__
sprintf (irq_buf, "%d", dev->irq);
#else
sprintf (irq_buf, "%s", __irq_itoa(dev->irq));
#endif
if (!request_irq(dev->irq, lynx_irq_handler, SA_SHIRQ,
PCILYNX_DRIVER_NAME, lynx)) {

16
drivers/message/fusion/mptbase.c
View file

@ -63,9 +63,6 @@
#ifdef CONFIG_MTRR
#include <asm/mtrr.h>
#endif
#ifdef __sparc__
#include <asm/irq.h> /* needed for __irq_itoa() proto */
#endif
#include "mptbase.h"
@ -1394,13 +1391,8 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
r = request_irq(pdev->irq, mpt_interrupt, SA_SHIRQ, ioc->name, ioc);
if (r < 0) {
#ifndef __sparc__
printk(MYIOC_s_ERR_FMT "Unable to allocate interrupt %d!\n",
ioc->name, pdev->irq);
#else
printk(MYIOC_s_ERR_FMT "Unable to allocate interrupt %s!\n",
ioc->name, __irq_itoa(pdev->irq));
#endif
list_del(&ioc->list);
iounmap(mem);
kfree(ioc);
@ -1412,11 +1404,7 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
pci_set_master(pdev); /* ?? */
pci_set_drvdata(pdev, ioc);
#ifndef __sparc__
dprintk((KERN_INFO MYNAM ": %s installed at interrupt %d\n", ioc->name, pdev->irq));
#else
dprintk((KERN_INFO MYNAM ": %s installed at interrupt %s\n", ioc->name, __irq_itoa(pdev->irq)));
#endif
}
/* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets.
@ -5647,11 +5635,7 @@ mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int sh
a[5], a[4], a[3], a[2], a[1], a[0]);
}
#ifndef __sparc__
y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq);
#else
y += sprintf(buffer+len+y, ", IRQ=%s", __irq_itoa(ioc->pci_irq));
#endif
if (!ioc->active)
y += sprintf(buffer+len+y, " (disabled)");

5
drivers/net/3c59x.c
View file

@ -1382,17 +1382,12 @@ static int __devinit vortex_probe1(struct device *gendev,
for (i = 0; i < 6; i++)
iowrite8(dev->dev_addr[i], ioaddr + i);
#ifdef __sparc__
if (print_info)
printk(", IRQ %s\n", __irq_itoa(dev->irq));
#else
if (print_info)
printk(", IRQ %d\n", dev->irq);
/* Tell them about an invalid IRQ. */
if (dev->irq <= 0 || dev->irq >= NR_IRQS)
printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
dev->irq);
#endif
EL3WINDOW(4);
step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;

6
drivers/net/acenic.c
View file

@ -579,11 +579,7 @@ static int __devinit acenic_probe_one(struct pci_dev *pdev,
}
printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
#ifdef __sparc__
printk("irq %s\n", __irq_itoa(pdev->irq));
#else
printk("irq %i\n", pdev->irq);
#endif
printk("irq %d\n", pdev->irq);
#ifdef CONFIG_ACENIC_OMIT_TIGON_I
if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {

5
drivers/net/sunhme.c
View file

@ -2221,13 +2221,8 @@ static int happy_meal_open(struct net_device *dev)
if (request_irq(dev->irq, &happy_meal_interrupt,
SA_SHIRQ, dev->name, (void *)dev)) {
HMD(("EAGAIN\n"));
#ifdef __sparc__
printk(KERN_ERR "happy_meal(SBUS): Can't order irq %s to go.\n",
__irq_itoa(dev->irq));
#else
printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
dev->irq);
#endif
return -EAGAIN;
}

2
drivers/net/sunlance.c
View file

@ -936,7 +936,7 @@ static int lance_open(struct net_device *dev)
if (request_irq(dev->irq, &lance_interrupt, SA_SHIRQ,
lancestr, (void *) dev)) {
printk(KERN_ERR "Lance: Can't get irq %s\n", __irq_itoa(dev->irq));
printk(KERN_ERR "Lance: Can't get irq %d\n", dev->irq);
return -EAGAIN;
}

4
drivers/sbus/char/cpwatchdog.c
View file

@ -304,8 +304,8 @@ static int wd_open(struct inode *inode, struct file *f)
SA_SHIRQ,
WD_OBPNAME,
(void *)wd_dev.regs)) {
printk("%s: Cannot register IRQ %s\n",
WD_OBPNAME, __irq_itoa(wd_dev.irq));
printk("%s: Cannot register IRQ %d\n",
WD_OBPNAME, wd_dev.irq);
return(-EBUSY);
}
wd_dev.initialized = 1;

2
drivers/sbus/char/uctrl.c
View file

@ -400,7 +400,7 @@ static int __init ts102_uctrl_init(void)
}
driver->regs->uctrl_intr = UCTRL_INTR_RXNE_REQ|UCTRL_INTR_RXNE_MSK;
printk("uctrl: 0x%x (irq %s)\n", driver->regs, __irq_itoa(driver->irq));
printk("uctrl: 0x%x (irq %d)\n", driver->regs, driver->irq);
uctrl_get_event_status();
uctrl_get_external_status();
return 0;

4
drivers/scsi/esp.c
View file

@ -821,8 +821,8 @@ static int __init esp_register_irq(struct esp *esp)
return -1;
}
printk("esp%d: IRQ %s ", esp->esp_id,
__irq_itoa(esp->ehost->irq));
printk("esp%d: IRQ %d ", esp->esp_id,
esp->ehost->irq);
return 0;
}

6
drivers/scsi/qlogicpti.c
View file

@ -725,7 +725,7 @@ static int __init qpti_register_irq(struct qlogicpti *qpti)
SA_SHIRQ, "Qlogic/PTI", qpti))
goto fail;
printk("qpti%d: IRQ %s ", qpti->qpti_id, __irq_itoa(qpti->irq));
printk("qpti%d: IRQ %d ", qpti->qpti_id, qpti->irq);
return 0;
@ -988,8 +988,8 @@ const char *qlogicpti_info(struct Scsi_Host *host)
static char buf[80];
struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata;
sprintf(buf, "PTI Qlogic,ISP SBUS SCSI irq %s regs at %p",
__irq_itoa(qpti->qhost->irq), qpti->qregs);
sprintf(buf, "PTI Qlogic,ISP SBUS SCSI irq %d regs at %p",
qpti->qhost->irq, qpti->qregs);
return buf;
}

6
drivers/scsi/sym53c8xx_2/sym_glue.c
View file

@ -54,14 +54,8 @@
#define NAME53C "sym53c"
#define NAME53C8XX "sym53c8xx"
/* SPARC just has to be different ... */
#ifdef __sparc__
#define IRQ_FMT "%s"
#define IRQ_PRM(x) __irq_itoa(x)
#else
#define IRQ_FMT "%d"
#define IRQ_PRM(x) (x)
#endif
struct sym_driver_setup sym_driver_setup = SYM_LINUX_DRIVER_SETUP;
unsigned int sym_debug_flags = 0;

4
drivers/serial/sunsu.c
View file

@ -1295,9 +1295,9 @@ static int __init sunsu_kbd_ms_init(struct uart_sunsu_port *up, int channel)
if (up->port.type == PORT_UNKNOWN)
return -1;
printk(KERN_INFO "su%d at 0x%p (irq = %s) is a %s\n",
printk(KERN_INFO "su%d at 0x%p (irq = %d) is a %s\n",
channel,
up->port.membase, __irq_itoa(up->port.irq),
up->port.membase, up->port.irq,
sunsu_type(&up->port));
#ifdef CONFIG_SERIO

4
drivers/serial/sunzilog.c
View file

@ -1540,8 +1540,8 @@ static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channe
up->cflag = B4800 | CS8 | CLOCAL | CREAD;
baud = 4800;
}
printk(KERN_INFO "zs%d at 0x%p (irq = %s) is a SunZilog\n",
channel, up->port.membase, __irq_itoa(zilog_irq));
printk(KERN_INFO "zs%d at 0x%p (irq = %d) is a SunZilog\n",
channel, up->port.membase, zilog_irq);
up->curregs[R15] = BRKIE;
brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);

12
drivers/usb/core/hcd.c
View file

@ -1826,24 +1826,16 @@ int usb_add_hcd(struct usb_hcd *hcd,
/* enable irqs just before we start the controller */
if (hcd->driver->irq) {
char buf[8], *bufp = buf;
#ifdef __sparc__
bufp = __irq_itoa(irqnum);
#else
sprintf(buf, "%d", irqnum);
#endif
snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
hcd->driver->description, hcd->self.busnum);
if ((retval = request_irq(irqnum, &usb_hcd_irq, irqflags,
hcd->irq_descr, hcd)) != 0) {
dev_err(hcd->self.controller,
"request interrupt %s failed\n", bufp);
"request interrupt %d failed\n", irqnum);
goto err_request_irq;
}
hcd->irq = irqnum;
dev_info(hcd->self.controller, "irq %s, %s 0x%08llx\n", bufp,
dev_info(hcd->self.controller, "irq %d, %s 0x%08llx\n", irqnum,
(hcd->driver->flags & HCD_MEMORY) ?
"io mem" : "io base",
(unsigned long long)hcd->rsrc_start);

11
drivers/usb/gadget/goku_udc.c
View file

@ -1850,7 +1850,6 @@ static int goku_probe(struct pci_dev *pdev, const struct pci_device_id *id)
unsigned long resource, len;
void __iomem *base = NULL;
int retval;
char buf [8], *bufp;
/* if you want to support more than one controller in a system,
* usb_gadget_driver_{register,unregister}() must change.
@ -1913,20 +1912,14 @@ static int goku_probe(struct pci_dev *pdev, const struct pci_device_id *id)
pci_set_drvdata(pdev, dev);
INFO(dev, "%s\n", driver_desc);
INFO(dev, "version: " DRIVER_VERSION " %s\n", dmastr());
#ifndef __sparc__
scnprintf(buf, sizeof buf, "%d", pdev->irq);
bufp = buf;
#else
bufp = __irq_itoa(pdev->irq);
#endif
INFO(dev, "irq %s, pci mem %p\n", bufp, base);
INFO(dev, "irq %d, pci mem %p\n", pdev->irq, base);
/* init to known state, then setup irqs */
udc_reset(dev);
udc_reinit (dev);
if (request_irq(pdev->irq, goku_irq, SA_SHIRQ/*|SA_SAMPLE_RANDOM*/,
driver_name, dev) != 0) {
DBG(dev, "request interrupt %s failed\n", bufp);
DBG(dev, "request interrupt %d failed\n", pdev->irq);
retval = -EBUSY;
goto done;
}

14
drivers/usb/gadget/net2280.c
View file

@ -2822,7 +2822,6 @@ static int net2280_probe (struct pci_dev *pdev, const struct pci_device_id *id)
unsigned long resource, len;
void __iomem *base = NULL;
int retval, i;
char buf [8], *bufp;
/* if you want to support more than one controller in a system,
* usb_gadget_driver_{register,unregister}() must change.
@ -2896,15 +2895,10 @@ static int net2280_probe (struct pci_dev *pdev, const struct pci_device_id *id)
retval = -ENODEV;
goto done;
}
#ifndef __sparc__
scnprintf (buf, sizeof buf, "%d", pdev->irq);
bufp = buf;
#else
bufp = __irq_itoa(pdev->irq);
#endif
if (request_irq (pdev->irq, net2280_irq, SA_SHIRQ, driver_name, dev)
!= 0) {
ERROR (dev, "request interrupt %s failed\n", bufp);
ERROR (dev, "request interrupt %d failed\n", pdev->irq);
retval = -EBUSY;
goto done;
}
@ -2953,8 +2947,8 @@ static int net2280_probe (struct pci_dev *pdev, const struct pci_device_id *id)
/* done */
INFO (dev, "%s\n", driver_desc);
INFO (dev, "irq %s, pci mem %p, chip rev %04x\n",
bufp, base, dev->chiprev);
INFO (dev, "irq %d, pci mem %p, chip rev %04x\n",
pdev->irq, base, dev->chiprev);
INFO (dev, "version: " DRIVER_VERSION "; dma %s\n",
use_dma
? (use_dma_chaining ? "chaining" : "enabled")

2
include/asm-sparc/irq.h
View file

@ -16,8 +16,6 @@
#define __irq_ino(irq) irq
#define __irq_pil(irq) irq
BTFIXUPDEF_CALL(char *, __irq_itoa, unsigned int)
#define __irq_itoa(irq) BTFIXUP_CALL(__irq_itoa)(irq)
#define NR_IRQS 16

8
include/asm-sparc/smp.h
View file

@ -145,6 +145,8 @@ static inline int hard_smp_processor_id(void)
#define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
#define prof_counter(__cpu) cpu_data(__cpu).counter
void smp_setup_cpu_possible_map(void);
#endif /* !(__ASSEMBLY__) */
/* Sparc specific messages. */
@ -161,7 +163,11 @@ static inline int hard_smp_processor_id(void)
#define MBOX_IDLECPU2 0xFD
#define MBOX_STOPCPU2 0xFE
#endif /* SMP */
#else /* SMP */
#define smp_setup_cpu_possible_map() do { } while (0)
#endif /* !(SMP) */
#define NO_PROC_ID 0xFF

3
include/asm-sparc/spinlock.h
View file

@ -154,6 +154,9 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
#define __raw_read_can_lock(rw) (!((rw)->lock & 0xff))
#define __raw_write_can_lock(rw) (!(rw)->lock)
#endif /* !(__ASSEMBLY__) */
#endif /* __SPARC_SPINLOCK_H */

19
include/asm-sparc64/cpudata.h
View file

@ -74,8 +74,10 @@ struct trap_per_cpu {
unsigned long tsb_huge;
unsigned long tsb_huge_temp;
/* Dcache line 8: Unused, needed to keep trap_block a power-of-2 in size. */
unsigned long __pad2[4];
/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */
unsigned int irq_worklist;
unsigned int __pad1;
unsigned long __pad2[3];
} __attribute__((aligned(64)));
extern struct trap_per_cpu trap_block[NR_CPUS];
extern void init_cur_cpu_trap(struct thread_info *);
@ -119,6 +121,7 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
#define TRAP_PER_CPU_CPU_LIST_PA 0xc8
#define TRAP_PER_CPU_TSB_HUGE 0xd0
#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8
#define TRAP_PER_CPU_IRQ_WORKLIST 0xe0
#define TRAP_BLOCK_SZ_SHIFT 8
@ -171,11 +174,8 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
#define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
__GET_CPUID(TMP) \
sethi %hi(__irq_work), DEST; \
sllx TMP, 6, TMP; \
or DEST, %lo(__irq_work), DEST; \
add DEST, TMP, DEST;
TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
add DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST;
/* Clobbers TMP, loads DEST with current thread info pointer. */
#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
@ -211,9 +211,10 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
#define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
sethi %hi(__irq_work), DEST; \
or DEST, %lo(__irq_work), DEST;
TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
add DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST;
#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \

2
include/asm-sparc64/hardirq.h
View file

@ -12,6 +12,8 @@
#define local_softirq_pending() \
(local_cpu_data().__softirq_pending)
void ack_bad_irq(unsigned int irq);
#define HARDIRQ_BITS 8
#endif /* !(__SPARC64_HARDIRQ_H) */

2
include/asm-sparc64/hw_irq.h
View file

@ -1,6 +1,6 @@
#ifndef __ASM_SPARC64_HW_IRQ_H
#define __ASM_SPARC64_HW_IRQ_H
/* Dummy include. */
extern void hw_resend_irq(struct hw_interrupt_type *handler, unsigned int virt_irq);
#endif

96
include/asm-sparc64/irq.h
View file

@ -15,58 +15,6 @@
#include <asm/pil.h>
#include <asm/ptrace.h>
struct ino_bucket;
#define MAX_IRQ_DESC_ACTION 4
struct irq_desc {
void (*pre_handler)(struct ino_bucket *, void *, void *);
void *pre_handler_arg1;
void *pre_handler_arg2;
u32 action_active_mask;
struct irqaction action[MAX_IRQ_DESC_ACTION];
};
/* You should not mess with this directly. That's the job of irq.c.
*
* If you make changes here, please update hand coded assembler of
* the vectored interrupt trap handler in entry.S -DaveM
*
* This is currently one DCACHE line, two buckets per L2 cache
* line. Keep this in mind please.
*/
struct ino_bucket {
/* Next handler in per-CPU PIL worklist. We know that
* bucket pointers have the high 32-bits clear, so to
* save space we only store the bits we need.
*/
/*0x00*/unsigned int irq_chain;
/* PIL to schedule this IVEC at. */
/*0x04*/unsigned char pil;
/* If an IVEC arrives while irq_info is NULL, we
* set this to notify request_irq() about the event.
*/
/*0x05*/unsigned char pending;
/* Miscellaneous flags. */
/*0x06*/unsigned char flags;
/* Currently unused. */
/*0x07*/unsigned char __pad;
/* Reference to IRQ descriptor for this bucket. */
/*0x08*/struct irq_desc *irq_info;
/* Sun5 Interrupt Clear Register. */
/*0x10*/unsigned long iclr;
/* Sun5 Interrupt Mapping Register. */
/*0x18*/unsigned long imap;
};
/* IMAP/ICLR register defines */
#define IMAP_VALID 0x80000000 /* IRQ Enabled */
#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
@ -84,36 +32,20 @@ struct ino_bucket {
#define ICLR_TRANSMIT 0x00000001 /* Transmit state */
#define ICLR_PENDING 0x00000003 /* Pending state */
/* Only 8-bits are available, be careful. -DaveM */
#define IBF_PCI 0x02 /* PSYCHO/SABRE/SCHIZO PCI interrupt. */
#define IBF_ACTIVE 0x04 /* Interrupt is active and has a handler.*/
#define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */
#define NUM_IVECS (IMAP_INR + 1)
extern struct ino_bucket ivector_table[NUM_IVECS];
#define __irq_ino(irq) \
(((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
#define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
static __inline__ char *__irq_itoa(unsigned int irq)
{
static char buff[16];
sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
return buff;
}
#define NR_IRQS 16
/* The largest number of unique interrupt sources we support.
* If this needs to ever be larger than 255, you need to change
* the type of ino_bucket->virt_irq as appropriate.
*
* ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq().
*/
#define NR_IRQS 255
extern void irq_install_pre_handler(int virt_irq,
void (*func)(unsigned int, void *, void *),
void *arg1, void *arg2);
#define irq_canonicalize(irq) (irq)
extern void disable_irq(unsigned int);
#define disable_irq_nosync disable_irq
extern void enable_irq(unsigned int);
extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags);
extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
static __inline__ void set_softint(unsigned long bits)
@ -139,8 +71,4 @@ static __inline__ unsigned long get_softint(void)
return retval;
}
struct irqaction;
struct pt_regs;
int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
#endif

7
include/asm-sparc64/pil.h
View file

@ -5,9 +5,9 @@
/* To avoid some locking problems, we hard allocate certain PILs
* for SMP cross call messages that must do a etrap/rtrap.
*
* A cli() does not block the cross call delivery, so when SMP
* locking is an issue we reschedule the event into a PIL interrupt
* which is blocked by cli().
* A local_irq_disable() does not block the cross call delivery, so
* when SMP locking is an issue we reschedule the event into a PIL
* interrupt which is blocked by local_irq_disable().
*
* In fact any XCALL which has to etrap/rtrap has a problem because
* it is difficult to prevent rtrap from running BH's, and that would
@ -17,6 +17,7 @@
#define PIL_SMP_RECEIVE_SIGNAL 2
#define PIL_SMP_CAPTURE 3
#define PIL_SMP_CTX_NEW_VERSION 4
#define PIL_DEVICE_IRQ 5
#ifndef __ASSEMBLY__
#define PIL_RESERVED(PIL) ((PIL) == PIL_SMP_CALL_FUNC || \

8
sound/sparc/amd7930.c
View file

@ -977,9 +977,9 @@ static int __init snd_amd7930_create(struct snd_card *card,
if (request_irq(irq_prop->pri, snd_amd7930_interrupt,
SA_INTERRUPT | SA_SHIRQ, "amd7930", amd)) {
snd_printk("amd7930-%d: Unable to grab IRQ %s\n",
snd_printk("amd7930-%d: Unable to grab IRQ %d\n",
dev,
__irq_itoa(irq_prop->pri));
irq_prop->pri);
snd_amd7930_free(amd);
return -EBUSY;
}
@ -1063,11 +1063,11 @@ static int __init amd7930_attach(int prom_node, struct sbus_dev *sdev)
strcpy(card->driver, "AMD7930");
strcpy(card->shortname, "Sun AMD7930");
sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s",
sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %d",
card->shortname,
rp->flags & 0xffL,
rp->start,
__irq_itoa(irq_prop.pri));
irq_prop.pri);
if ((err = snd_amd7930_create(card, sdev, rp, reg_prop.reg_size,
&irq_prop, dev, &amd)) < 0)

13
sound/sparc/cs4231.c
View file

@ -2003,9 +2003,8 @@ static int __init snd_cs4231_sbus_create(struct snd_card *card,
if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
SA_SHIRQ, "cs4231", chip)) {
snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %s\n",
dev,
__irq_itoa(sdev->irqs[0]));
snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
dev, sdev->irqs[0]);
snd_cs4231_sbus_free(chip);
return -EBUSY;
}
@ -2038,11 +2037,11 @@ static int __init cs4231_sbus_attach(struct sbus_dev *sdev)
if (err)
return err;
sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s",
sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %d",
card->shortname,
rp->flags & 0xffL,
rp->start,
__irq_itoa(sdev->irqs[0]));
sdev->irqs[0]);
if ((err = snd_cs4231_sbus_create(card, sdev, dev, &cp)) < 0) {
snd_card_free(card);
@ -2244,10 +2243,10 @@ static int __init cs4231_ebus_attach(struct linux_ebus_device *edev)
if (err)
return err;
sprintf(card->longname, "%s at 0x%lx, irq %s",
sprintf(card->longname, "%s at 0x%lx, irq %d",
card->shortname,
edev->resource[0].start,
__irq_itoa(edev->irqs[0]));
edev->irqs[0]);
if ((err = snd_cs4231_ebus_create(card, edev, dev, &chip)) < 0) {
snd_card_free(card);

4
sound/sparc/dbri.c
View file

@ -2645,9 +2645,9 @@ static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
strcpy(card->driver, "DBRI");
strcpy(card->shortname, "Sun DBRI");
rp = &sdev->resource[0];
sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s",
sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %d",
card->shortname,
rp->flags & 0xffL, rp->start, __irq_itoa(irq.pri));
rp->flags & 0xffL, rp->start, irq.pri);
if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
snd_card_free(card);