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https://github.com/torvalds/linux
synced 2024-09-25 14:01:32 +00:00
sh: Kill off segment-based d-cache flushing on SH-4.
This kills off the unrolled segment based flushers on SH-4 and switches over to a generic unrolled approach derived from the writethrough segment flusher. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
31c9efde78
commit
bd6df57481
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@ -29,14 +29,6 @@
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static void __flush_cache_4096(unsigned long addr, unsigned long phys,
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unsigned long exec_offset);
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/*
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* This is initialised here to ensure that it is not placed in the BSS. If
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* that were to happen, note that cache_init gets called before the BSS is
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* cleared, so this would get nulled out which would be hopeless.
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*/
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static void (*__flush_dcache_segment_fn)(unsigned long, unsigned long) =
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(void (*)(unsigned long, unsigned long))0xdeadbeef;
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/*
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* Write back the range of D-cache, and purge the I-cache.
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*
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@ -158,10 +150,27 @@ static void __uses_jump_to_uncached flush_icache_all(void)
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local_irq_restore(flags);
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}
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static inline void flush_dcache_all(void)
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static void flush_dcache_all(void)
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{
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(*__flush_dcache_segment_fn)(0UL, boot_cpu_data.dcache.way_size);
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wmb();
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unsigned long addr, end_addr, entry_offset;
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end_addr = CACHE_OC_ADDRESS_ARRAY +
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(current_cpu_data.dcache.sets <<
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current_cpu_data.dcache.entry_shift) *
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current_cpu_data.dcache.ways;
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entry_offset = 1 << current_cpu_data.dcache.entry_shift;
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for (addr = CACHE_OC_ADDRESS_ARRAY; addr < end_addr; ) {
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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}
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}
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static void sh4_flush_cache_all(void *unused)
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@ -347,245 +356,6 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys,
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} while (--way_count != 0);
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}
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/*
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* Break the 1, 2 and 4 way variants of this out into separate functions to
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* avoid nearly all the overhead of having the conditional stuff in the function
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* bodies (+ the 1 and 2 way cases avoid saving any registers too).
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*
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* We want to eliminate unnecessary bus transactions, so this code uses
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* a non-obvious technique.
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*
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* Loop over a cache way sized block of, one cache line at a time. For each
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* line, use movca.a to cause the current cache line contents to be written
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* back, but without reading anything from main memory. However this has the
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* side effect that the cache is now caching that memory location. So follow
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* this with a cache invalidate to mark the cache line invalid. And do all
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* this with interrupts disabled, to avoid the cache line being accidently
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* evicted while it is holding garbage.
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*
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* This also breaks in a number of circumstances:
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* - if there are modifications to the region of memory just above
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* empty_zero_page (for example because a breakpoint has been placed
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* there), then these can be lost.
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*
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* This is because the the memory address which the cache temporarily
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* caches in the above description is empty_zero_page. So the
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* movca.l hits the cache (it is assumed that it misses, or at least
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* isn't dirty), modifies the line and then invalidates it, losing the
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* required change.
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*
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* - If caches are disabled or configured in write-through mode, then
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* the movca.l writes garbage directly into memory.
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*/
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static void __flush_dcache_segment_writethrough(unsigned long start,
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unsigned long extent_per_way)
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{
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unsigned long addr;
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int i;
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addr = CACHE_OC_ADDRESS_ARRAY | (start & cpu_data->dcache.entry_mask);
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while (extent_per_way) {
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for (i = 0; i < cpu_data->dcache.ways; i++)
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__raw_writel(0, addr + cpu_data->dcache.way_incr * i);
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addr += cpu_data->dcache.linesz;
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extent_per_way -= cpu_data->dcache.linesz;
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}
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}
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static void __flush_dcache_segment_1way(unsigned long start,
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unsigned long extent_per_way)
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{
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unsigned long orig_sr, sr_with_bl;
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unsigned long base_addr;
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unsigned long way_incr, linesz, way_size;
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struct cache_info *dcache;
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register unsigned long a0, a0e;
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asm volatile("stc sr, %0" : "=r" (orig_sr));
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sr_with_bl = orig_sr | (1<<28);
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base_addr = ((unsigned long)&empty_zero_page[0]);
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/*
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* The previous code aligned base_addr to 16k, i.e. the way_size of all
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* existing SH-4 D-caches. Whilst I don't see a need to have this
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* aligned to any better than the cache line size (which it will be
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* anyway by construction), let's align it to at least the way_size of
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* any existing or conceivable SH-4 D-cache. -- RPC
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*/
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base_addr = ((base_addr >> 16) << 16);
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base_addr |= start;
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dcache = &boot_cpu_data.dcache;
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linesz = dcache->linesz;
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way_incr = dcache->way_incr;
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way_size = dcache->way_size;
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a0 = base_addr;
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a0e = base_addr + extent_per_way;
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do {
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asm volatile("ldc %0, sr" : : "r" (sr_with_bl));
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asm volatile("movca.l r0, @%0\n\t"
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"ocbi @%0" : : "r" (a0));
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a0 += linesz;
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asm volatile("movca.l r0, @%0\n\t"
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"ocbi @%0" : : "r" (a0));
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a0 += linesz;
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asm volatile("movca.l r0, @%0\n\t"
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"ocbi @%0" : : "r" (a0));
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a0 += linesz;
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asm volatile("movca.l r0, @%0\n\t"
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"ocbi @%0" : : "r" (a0));
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asm volatile("ldc %0, sr" : : "r" (orig_sr));
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a0 += linesz;
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} while (a0 < a0e);
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}
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static void __flush_dcache_segment_2way(unsigned long start,
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unsigned long extent_per_way)
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{
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unsigned long orig_sr, sr_with_bl;
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unsigned long base_addr;
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unsigned long way_incr, linesz, way_size;
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struct cache_info *dcache;
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register unsigned long a0, a1, a0e;
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asm volatile("stc sr, %0" : "=r" (orig_sr));
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sr_with_bl = orig_sr | (1<<28);
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base_addr = ((unsigned long)&empty_zero_page[0]);
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/* See comment under 1-way above */
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base_addr = ((base_addr >> 16) << 16);
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base_addr |= start;
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dcache = &boot_cpu_data.dcache;
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linesz = dcache->linesz;
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way_incr = dcache->way_incr;
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way_size = dcache->way_size;
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a0 = base_addr;
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a1 = a0 + way_incr;
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a0e = base_addr + extent_per_way;
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do {
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asm volatile("ldc %0, sr" : : "r" (sr_with_bl));
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asm volatile("movca.l r0, @%0\n\t"
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"movca.l r0, @%1\n\t"
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"ocbi @%0\n\t"
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"ocbi @%1" : :
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"r" (a0), "r" (a1));
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a0 += linesz;
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a1 += linesz;
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asm volatile("movca.l r0, @%0\n\t"
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"movca.l r0, @%1\n\t"
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"ocbi @%0\n\t"
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"ocbi @%1" : :
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"r" (a0), "r" (a1));
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a0 += linesz;
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a1 += linesz;
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asm volatile("movca.l r0, @%0\n\t"
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"movca.l r0, @%1\n\t"
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"ocbi @%0\n\t"
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"ocbi @%1" : :
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"r" (a0), "r" (a1));
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a0 += linesz;
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a1 += linesz;
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asm volatile("movca.l r0, @%0\n\t"
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"movca.l r0, @%1\n\t"
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"ocbi @%0\n\t"
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"ocbi @%1" : :
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"r" (a0), "r" (a1));
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asm volatile("ldc %0, sr" : : "r" (orig_sr));
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a0 += linesz;
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a1 += linesz;
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} while (a0 < a0e);
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}
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static void __flush_dcache_segment_4way(unsigned long start,
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unsigned long extent_per_way)
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{
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unsigned long orig_sr, sr_with_bl;
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unsigned long base_addr;
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unsigned long way_incr, linesz, way_size;
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struct cache_info *dcache;
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register unsigned long a0, a1, a2, a3, a0e;
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asm volatile("stc sr, %0" : "=r" (orig_sr));
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sr_with_bl = orig_sr | (1<<28);
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base_addr = ((unsigned long)&empty_zero_page[0]);
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/* See comment under 1-way above */
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base_addr = ((base_addr >> 16) << 16);
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base_addr |= start;
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dcache = &boot_cpu_data.dcache;
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linesz = dcache->linesz;
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way_incr = dcache->way_incr;
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way_size = dcache->way_size;
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a0 = base_addr;
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a1 = a0 + way_incr;
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a2 = a1 + way_incr;
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a3 = a2 + way_incr;
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a0e = base_addr + extent_per_way;
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do {
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asm volatile("ldc %0, sr" : : "r" (sr_with_bl));
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asm volatile("movca.l r0, @%0\n\t"
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"movca.l r0, @%1\n\t"
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"movca.l r0, @%2\n\t"
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"movca.l r0, @%3\n\t"
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"ocbi @%0\n\t"
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"ocbi @%1\n\t"
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"ocbi @%2\n\t"
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"ocbi @%3\n\t" : :
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"r" (a0), "r" (a1), "r" (a2), "r" (a3));
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a0 += linesz;
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a1 += linesz;
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a2 += linesz;
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a3 += linesz;
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asm volatile("movca.l r0, @%0\n\t"
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"movca.l r0, @%1\n\t"
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"movca.l r0, @%2\n\t"
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"movca.l r0, @%3\n\t"
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"ocbi @%0\n\t"
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"ocbi @%1\n\t"
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"ocbi @%2\n\t"
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"ocbi @%3\n\t" : :
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"r" (a0), "r" (a1), "r" (a2), "r" (a3));
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a0 += linesz;
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a1 += linesz;
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a2 += linesz;
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a3 += linesz;
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asm volatile("movca.l r0, @%0\n\t"
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"movca.l r0, @%1\n\t"
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"movca.l r0, @%2\n\t"
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"movca.l r0, @%3\n\t"
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"ocbi @%0\n\t"
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"ocbi @%1\n\t"
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"ocbi @%2\n\t"
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"ocbi @%3\n\t" : :
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"r" (a0), "r" (a1), "r" (a2), "r" (a3));
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a0 += linesz;
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a1 += linesz;
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a2 += linesz;
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a3 += linesz;
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asm volatile("movca.l r0, @%0\n\t"
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"movca.l r0, @%1\n\t"
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"movca.l r0, @%2\n\t"
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"movca.l r0, @%3\n\t"
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"ocbi @%0\n\t"
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"ocbi @%1\n\t"
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"ocbi @%2\n\t"
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"ocbi @%3\n\t" : :
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"r" (a0), "r" (a1), "r" (a2), "r" (a3));
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asm volatile("ldc %0, sr" : : "r" (orig_sr));
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a0 += linesz;
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a1 += linesz;
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a2 += linesz;
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a3 += linesz;
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} while (a0 < a0e);
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}
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extern void __weak sh4__flush_region_init(void);
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/*
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@ -593,32 +363,11 @@ extern void __weak sh4__flush_region_init(void);
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*/
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void __init sh4_cache_init(void)
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{
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unsigned int wt_enabled = !!(__raw_readl(CCR) & CCR_CACHE_WT);
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printk("PVR=%08x CVR=%08x PRR=%08x\n",
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ctrl_inl(CCN_PVR),
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ctrl_inl(CCN_CVR),
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ctrl_inl(CCN_PRR));
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if (wt_enabled)
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__flush_dcache_segment_fn = __flush_dcache_segment_writethrough;
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else {
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switch (boot_cpu_data.dcache.ways) {
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case 1:
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__flush_dcache_segment_fn = __flush_dcache_segment_1way;
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break;
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case 2:
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__flush_dcache_segment_fn = __flush_dcache_segment_2way;
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break;
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case 4:
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__flush_dcache_segment_fn = __flush_dcache_segment_4way;
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break;
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default:
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panic("unknown number of cache ways\n");
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break;
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}
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}
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local_flush_icache_range = sh4_flush_icache_range;
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local_flush_dcache_page = sh4_flush_dcache_page;
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local_flush_cache_all = sh4_flush_cache_all;
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