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powerpc: Handle VSX alignment faults correctly in little-endian mode
This patch fixes the handling of VSX alignment faults in little-endian mode (the current code assumes the processor is in big-endian mode). The patch also makes the handlers clear the top 8 bytes of the register when handling an 8 byte VSX load. This is based on 2.6.32. Signed-off-by: Neil Campbell <neilc@linux.vnet.ibm.com> Cc: <stable@kernel.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -642,10 +642,14 @@ static int emulate_spe(struct pt_regs *regs, unsigned int reg,
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*/
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static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
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unsigned int areg, struct pt_regs *regs,
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unsigned int flags, unsigned int length)
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unsigned int flags, unsigned int length,
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unsigned int elsize)
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{
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char *ptr;
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unsigned long *lptr;
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int ret = 0;
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int sw = 0;
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int i, j;
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flush_vsx_to_thread(current);
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@ -654,19 +658,35 @@ static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
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else
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ptr = (char *) ¤t->thread.vr[reg - 32];
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if (flags & ST)
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ret = __copy_to_user(addr, ptr, length);
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else {
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if (flags & SPLT){
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ret = __copy_from_user(ptr, addr, length);
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ptr += length;
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lptr = (unsigned long *) ptr;
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if (flags & SW)
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sw = elsize-1;
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for (j = 0; j < length; j += elsize) {
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for (i = 0; i < elsize; ++i) {
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if (flags & ST)
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ret |= __put_user(ptr[i^sw], addr + i);
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else
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ret |= __get_user(ptr[i^sw], addr + i);
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}
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ret |= __copy_from_user(ptr, addr, length);
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ptr += elsize;
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addr += elsize;
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}
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if (flags & U)
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regs->gpr[areg] = regs->dar;
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if (ret)
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if (!ret) {
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if (flags & U)
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regs->gpr[areg] = regs->dar;
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/* Splat load copies the same data to top and bottom 8 bytes */
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if (flags & SPLT)
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lptr[1] = lptr[0];
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/* For 8 byte loads, zero the top 8 bytes */
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else if (!(flags & ST) && (8 == length))
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lptr[1] = 0;
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} else
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return -EFAULT;
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return 1;
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}
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#endif
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@ -767,16 +787,25 @@ int fix_alignment(struct pt_regs *regs)
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#ifdef CONFIG_VSX
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if ((instruction & 0xfc00003e) == 0x7c000018) {
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/* Additional register addressing bit (64 VSX vs 32 FPR/GPR */
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unsigned int elsize;
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/* Additional register addressing bit (64 VSX vs 32 FPR/GPR) */
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reg |= (instruction & 0x1) << 5;
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/* Simple inline decoder instead of a table */
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/* VSX has only 8 and 16 byte memory accesses */
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nb = 8;
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if (instruction & 0x200)
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nb = 16;
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else if (instruction & 0x080)
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nb = 8;
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else
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nb = 4;
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/* Vector stores in little-endian mode swap individual
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elements, so process them separately */
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elsize = 4;
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if (instruction & 0x80)
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elsize = 8;
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flags = 0;
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if (regs->msr & MSR_LE)
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flags |= SW;
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if (instruction & 0x100)
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flags |= ST;
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if (instruction & 0x040)
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@ -787,7 +816,7 @@ int fix_alignment(struct pt_regs *regs)
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nb = 8;
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}
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PPC_WARN_ALIGNMENT(vsx, regs);
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return emulate_vsx(addr, reg, areg, regs, flags, nb);
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return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize);
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}
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#endif
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/* A size of 0 indicates an instruction we don't support, with
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