HiSilicon driver updates for v6.6

- Add HCCS driver for HiSilicon Kunpeng SoC and document the sysfs description
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Merge tag 'hisi-drivers-for-6.6' of https://github.com/hisilicon/linux-hisi into soc/drivers

HiSilicon driver updates for v6.6

- Add HCCS driver for HiSilicon Kunpeng SoC and document the sysfs description

* tag 'hisi-drivers-for-6.6' of https://github.com/hisilicon/linux-hisi:
  doc: soc: hisilicon: Add Kunpeng HCCS driver documentation
  soc: hisilicon: add sysfs entry to query information of HCCS
  soc: hisilicon: Support HCCS driver on Kunpeng SoC

Link: https://lore.kernel.org/r/64D605DE.2070303@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-08-12 12:10:46 +02:00
commit bb2974ffff
8 changed files with 1578 additions and 0 deletions

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@ -0,0 +1,81 @@
What: /sys/devices/platform/HISI04Bx:00/chipX/all_linked
What: /sys/devices/platform/HISI04Bx:00/chipX/linked_full_lane
What: /sys/devices/platform/HISI04Bx:00/chipX/crc_err_cnt
Date: November 2023
KernelVersion: 6.6
Contact: Huisong Li <lihuisong@huawei.org>
Description:
The /sys/devices/platform/HISI04Bx:00/chipX/ directory
contains read-only attributes exposing some summarization
information of all HCCS ports under a specified chip.
The X in 'chipX' indicates the Xth chip on platform.
There are following attributes in this directory:
================= ==== =========================================
all_linked: (RO) if all enabled ports on this chip are
linked (bool).
linked_full_lane: (RO) if all linked ports on this chip are full
lane (bool).
crc_err_cnt: (RO) total CRC err count for all ports on this
chip.
================= ==== =========================================
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/all_linked
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/linked_full_lane
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/crc_err_cnt
Date: November 2023
KernelVersion: 6.6
Contact: Huisong Li <lihuisong@huawei.org>
Description:
The /sys/devices/platform/HISI04Bx:00/chipX/dieY/ directory
contains read-only attributes exposing some summarization
information of all HCCS ports under a specified die.
The Y in 'dieY' indicates the hardware id of the die on chip who
has chip id X.
There are following attributes in this directory:
================= ==== =========================================
all_linked: (RO) if all enabled ports on this die are
linked (bool).
linked_full_lane: (RO) if all linked ports on this die are full
lane (bool).
crc_err_cnt: (RO) total CRC err count for all ports on this
die.
================= ==== =========================================
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/type
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mode
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/enable
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/cur_lane_num
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/link_fsm
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mask
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/crc_err_cnt
Date: November 2023
KernelVersion: 6.6
Contact: Huisong Li <lihuisong@huawei.org>
Description:
The /sys/devices/platform/HISI04Bx/chipX/dieX/hccsN/ directory
contains read-only attributes exposing information about
a HCCS port. The N value in 'hccsN' indicates this port id.
The X in 'chipX' indicates the ID of the chip to which the
HCCS port belongs. For example, X ranges from to 'n - 1' if the
chip number on platform is n.
The Y in 'dieY' indicates the hardware id of the die to which
the hccs port belongs.
Note: type, lane_mode and enable are fixed attributes on running
platform.
The HCCS port have the following attributes:
============= ==== =============================================
type: (RO) port type (string), e.g. HCCS-v1 -> H32
lane_mode: (RO) the lane mode of this port (string), e.g. x8
enable: (RO) indicate if this port is enabled (bool).
cur_lane_num: (RO) current lane number of this port.
link_fsm: (RO) link finite state machine of this port.
lane_mask: (RO) current lane mask of this port, every bit
indicates a lane.
crc_err_cnt: (RO) CRC err count on this port.
============= ==== =============================================

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@ -9327,6 +9327,13 @@ W: https://www.hisilicon.com
F: Documentation/devicetree/bindings/i2c/hisilicon,ascend910-i2c.yaml
F: drivers/i2c/busses/i2c-hisi.c
HISILICON KUNPENG SOC HCCS DRIVER
M: Huisong Li <lihuisong@huawei.com>
S: Maintained
F: Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs
F: drivers/soc/hisilicon/kunpeng_hccs.c
F: drivers/soc/hisilicon/kunpeng_hccs.h
HISILICON LPC BUS DRIVER
M: Jay Fang <f.fangjian@huawei.com>
S: Maintained

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@ -10,6 +10,7 @@ source "drivers/soc/bcm/Kconfig"
source "drivers/soc/canaan/Kconfig"
source "drivers/soc/fsl/Kconfig"
source "drivers/soc/fujitsu/Kconfig"
source "drivers/soc/hisilicon/Kconfig"
source "drivers/soc/imx/Kconfig"
source "drivers/soc/ixp4xx/Kconfig"
source "drivers/soc/litex/Kconfig"

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@ -13,6 +13,7 @@ obj-$(CONFIG_MACH_DOVE) += dove/
obj-y += fsl/
obj-y += fujitsu/
obj-$(CONFIG_ARCH_GEMINI) += gemini/
obj-y += hisilicon/
obj-y += imx/
obj-y += ixp4xx/
obj-$(CONFIG_SOC_XWAY) += lantiq/

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@ -0,0 +1,20 @@
# SPDX-License-Identifier: GPL-2.0-only
menu "Hisilicon SoC drivers"
depends on ARCH_HISI || COMPILE_TEST
config KUNPENG_HCCS
tristate "HCCS driver on Kunpeng SoC"
depends on ACPI
depends on ARM64 || COMPILE_TEST
help
The Huawei Cache Coherence System (HCCS) is a multi-chip
interconnection bus protocol.
The performance of application may be affected if some HCCS
ports are not in full lane status, have a large number of CRC
errors and so on.
Say M here if you want to include support for querying the
health status and port information of HCCS on Kunpeng SoC.
endmenu

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@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_KUNPENG_HCCS) += kunpeng_hccs.o

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/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2023 Hisilicon Limited. */
#ifndef __KUNPENG_HCCS_H__
#define __KUNPENG_HCCS_H__
/*
* |--------------- Chip0 ---------------|---------------- ChipN -------------|
* |--------Die0-------|--------DieN-------|--------Die0-------|-------DieN-------|
* | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 |P0 | P1 | P2 | P3 |
*/
/*
* This value cannot be 255, otherwise the loop of the multi-BD communication
* case cannot end.
*/
#define HCCS_DIE_MAX_PORT_ID 254
struct hccs_port_info {
u8 port_id;
u8 port_type;
u8 lane_mode;
bool enable; /* if the port is enabled */
struct kobject kobj;
bool dir_created;
struct hccs_die_info *die; /* point to the die the port is located */
};
struct hccs_die_info {
u8 die_id;
u8 port_num;
u8 min_port_id;
u8 max_port_id;
struct hccs_port_info *ports;
struct kobject kobj;
bool dir_created;
struct hccs_chip_info *chip; /* point to the chip the die is located */
};
struct hccs_chip_info {
u8 chip_id;
u8 die_num;
struct hccs_die_info *dies;
struct kobject kobj;
struct hccs_dev *hdev;
};
struct hccs_mbox_client_info {
struct mbox_client client;
struct mbox_chan *mbox_chan;
struct pcc_mbox_chan *pcc_chan;
u64 deadline_us;
void *pcc_comm_addr;
};
struct hccs_dev {
struct device *dev;
struct acpi_device *acpi_dev;
u64 caps;
u8 chip_num;
struct hccs_chip_info *chips;
u8 chan_id;
struct mutex lock;
struct hccs_mbox_client_info cl_info;
};
#define HCCS_SERDES_MODULE_CODE 0x32
enum hccs_subcmd_type {
HCCS_GET_CHIP_NUM = 0x1,
HCCS_GET_DIE_NUM,
HCCS_GET_DIE_INFO,
HCCS_GET_DIE_PORT_INFO,
HCCS_GET_DEV_CAP,
HCCS_GET_PORT_LINK_STATUS,
HCCS_GET_PORT_CRC_ERR_CNT,
HCCS_GET_DIE_PORTS_LANE_STA,
HCCS_GET_DIE_PORTS_LINK_STA,
HCCS_GET_DIE_PORTS_CRC_ERR_CNT,
HCCS_SUB_CMD_MAX = 255,
};
struct hccs_die_num_req_param {
u8 chip_id;
};
struct hccs_die_info_req_param {
u8 chip_id;
u8 die_idx;
};
struct hccs_die_info_rsp_data {
u8 die_id;
u8 port_num;
u8 min_port_id;
u8 max_port_id;
};
struct hccs_port_attr {
u8 port_id;
u8 port_type;
u8 lane_mode;
u8 enable : 1; /* if the port is enabled */
u16 rsv[2];
};
/*
* The common command request for getting the information of all HCCS port on
* specified DIE.
*/
struct hccs_die_comm_req_param {
u8 chip_id;
u8 die_id; /* id in hardware */
};
/* The common command request for getting the information of a specific port */
struct hccs_port_comm_req_param {
u8 chip_id;
u8 die_id;
u8 port_id;
};
#define HCCS_PORT_RESET 1
#define HCCS_PORT_SETUP 2
#define HCCS_PORT_CONFIG 3
#define HCCS_PORT_READY 4
struct hccs_link_status {
u8 lane_mask; /* indicate which lanes are used. */
u8 link_fsm : 3; /* link fsm, 1: reset 2: setup 3: config 4: link-up */
u8 lane_num : 5; /* current lane number */
};
struct hccs_req_head {
u8 module_code; /* set to 0x32 for serdes */
u8 start_id;
u8 rsv[2];
};
struct hccs_rsp_head {
u8 data_len;
u8 next_id;
u8 rsv[2];
};
struct hccs_fw_inner_head {
u8 retStatus; /* 0: success, other: failure */
u8 rsv[7];
};
#define HCCS_PCC_SHARE_MEM_BYTES 64
#define HCCS_FW_INNER_HEAD_BYTES 8
#define HCCS_RSP_HEAD_BYTES 4
#define HCCS_MAX_RSP_DATA_BYTES (HCCS_PCC_SHARE_MEM_BYTES - \
HCCS_FW_INNER_HEAD_BYTES - \
HCCS_RSP_HEAD_BYTES)
#define HCCS_MAX_RSP_DATA_SIZE_MAX (HCCS_MAX_RSP_DATA_BYTES / 4)
/*
* Note: Actual available size of data field also depands on the PCC header
* bytes of the specific type. Driver needs to copy the response data in the
* communication space based on the real length.
*/
struct hccs_rsp_desc {
struct hccs_fw_inner_head fw_inner_head; /* 8 Bytes */
struct hccs_rsp_head rsp_head; /* 4 Bytes */
u32 data[HCCS_MAX_RSP_DATA_SIZE_MAX];
};
#define HCCS_REQ_HEAD_BYTES 4
#define HCCS_MAX_REQ_DATA_BYTES (HCCS_PCC_SHARE_MEM_BYTES - \
HCCS_REQ_HEAD_BYTES)
#define HCCS_MAX_REQ_DATA_SIZE_MAX (HCCS_MAX_REQ_DATA_BYTES / 4)
/*
* Note: Actual available size of data field also depands on the PCC header
* bytes of the specific type. Driver needs to copy the request data to the
* communication space based on the real length.
*/
struct hccs_req_desc {
struct hccs_req_head req_head; /* 4 Bytes */
u32 data[HCCS_MAX_REQ_DATA_SIZE_MAX];
};
struct hccs_desc {
union {
struct hccs_req_desc req;
struct hccs_rsp_desc rsp;
};
};
#endif /* __KUNPENG_HCCS_H__ */