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ARM: tegra: Enable PCIe controller on Beaver

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PCIe lane 0 is connected to an onboard Gigabit Ethernet (RTL8168evl) and
lane 4 is routed to the board's miniPCIe slot.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Thierry Reding 2013-08-09 16:49:28 +02:00 committed by Stephen Warren
parent 89e7ada416
commit bb034cb5eb
1 changed files with 21 additions and 0 deletions
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21
arch/arm/boot/dts/tegra30-beaver.dts
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@ -10,6 +10,27 @@ memory {
reg = <0x80000000 0x7ff00000>;
};
pcie-controller {
status = "okay";
pex-clk-supply = <&sys_3v3_pexs_reg>;
vdd-supply = <&ldo1_reg>;
avdd-supply = <&ldo2_reg>;
pci@1,0 {
status = "okay";
nvidia,num-lanes = <4>;
};
pci@2,0 {
status = "okay";
nvidia,num-lanes = <1>;
};
pci@3,0 {
nvidia,num-lanes = <1>;
};
};
host1x {
hdmi {
status = "okay";