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https://github.com/torvalds/linux
synced 2024-09-21 19:47:35 +00:00
ALSA: hda/ca0132 - Add AE-5 pre-init and ca0113 functions
This patch adds AE-5 pre-init functions that happen before the main ca0132_alt_init, and gives functions related to the ca0113 a ca0113 prefix instead of ca0132. It also adds functions to write to the 8051's SFRs, and to write the special ca0113 commands for the AE-5. Signed-off-by: Connor McAdams <conmanx360@gmail.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Connor McAdams
Takashi Iwai
parent
ce7154480c
commit
b9b413450c
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@ -1482,6 +1482,20 @@ static void chipio_set_conn_rate(struct hda_codec *codec,
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rate);
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}
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/*
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* Writes to the 8051's internal address space directly instead of indirectly,
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* giving access to the special function registers located at addresses
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* 0x80-0xFF.
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*/
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static void chipio_8051_write_direct(struct hda_codec *codec,
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unsigned int addr, unsigned int data)
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{
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unsigned int verb;
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verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
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}
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/*
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* Enable clocks.
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*/
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@ -3117,7 +3131,9 @@ static bool dspload_wait_loaded(struct hda_codec *codec)
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}
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/*
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* Setup GPIO for the other variants of Core3D.
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* ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
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* based cards, and has a second mmio region, region2, that's used for special
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* commands.
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*/
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/*
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@ -3125,8 +3141,11 @@ static bool dspload_wait_loaded(struct hda_codec *codec)
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* the mmio address 0x320 is used to set GPIO pins. The format for the data
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* The first eight bits are just the number of the pin. So far, I've only seen
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* this number go to 7.
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* AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
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* of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
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* then off to send that bit.
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*/
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static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
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static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
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bool enable)
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{
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struct ca0132_spec *spec = codec->spec;
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@ -3138,6 +3157,54 @@ static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
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writew(gpio_data, spec->mem_base + 0x320);
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}
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/*
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* Special pci region2 commands that are only used by the AE-5. They follow
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* a set format, and require reads at certain points to seemingly 'clear'
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* the response data. My first tests didn't do these reads, and would cause
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* the card to get locked up until the memory was read. These commands
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* seem to work with three distinct values that I've taken to calling group,
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* target-id, and value.
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*/
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static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
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unsigned int target, unsigned int value)
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{
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struct ca0132_spec *spec = codec->spec;
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unsigned int write_val;
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writel(0x0000007e, spec->mem_base + 0x210);
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readl(spec->mem_base + 0x210);
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writel(0x0000005a, spec->mem_base + 0x210);
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readl(spec->mem_base + 0x210);
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readl(spec->mem_base + 0x210);
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writel(0x00800005, spec->mem_base + 0x20c);
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writel(group, spec->mem_base + 0x804);
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writel(0x00800005, spec->mem_base + 0x20c);
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write_val = (target & 0xff);
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write_val |= (value << 8);
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writel(write_val, spec->mem_base + 0x204);
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/*
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* Need delay here or else it goes too fast and works inconsistently.
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*/
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msleep(20);
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readl(spec->mem_base + 0x860);
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readl(spec->mem_base + 0x854);
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readl(spec->mem_base + 0x840);
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writel(0x00800004, spec->mem_base + 0x20c);
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writel(0x00000000, spec->mem_base + 0x210);
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readl(spec->mem_base + 0x210);
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readl(spec->mem_base + 0x210);
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}
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/*
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* Setup GPIO for the other variants of Core3D.
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*/
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/*
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* Sets up the GPIO pins so that they are discoverable. If this isn't done,
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* the card shows as having no GPIO pins.
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@ -4013,9 +4080,9 @@ static int ca0132_alt_select_out(struct hda_codec *codec)
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/*speaker out config*/
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switch (spec->quirk) {
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case QUIRK_SBZ:
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ca0132_mmio_gpio_set(codec, 7, false);
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ca0132_mmio_gpio_set(codec, 4, true);
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ca0132_mmio_gpio_set(codec, 1, true);
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ca0113_mmio_gpio_set(codec, 7, false);
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ca0113_mmio_gpio_set(codec, 4, true);
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ca0113_mmio_gpio_set(codec, 1, true);
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chipio_set_control_param(codec, 0x0D, 0x18);
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break;
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case QUIRK_R3DI:
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@ -4024,7 +4091,7 @@ static int ca0132_alt_select_out(struct hda_codec *codec)
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break;
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case QUIRK_R3D:
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chipio_set_control_param(codec, 0x0D, 0x24);
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ca0132_mmio_gpio_set(codec, 1, true);
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ca0113_mmio_gpio_set(codec, 1, true);
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break;
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}
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@ -4053,9 +4120,9 @@ static int ca0132_alt_select_out(struct hda_codec *codec)
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/* Headphone out config*/
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switch (spec->quirk) {
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case QUIRK_SBZ:
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ca0132_mmio_gpio_set(codec, 7, true);
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ca0132_mmio_gpio_set(codec, 4, true);
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ca0132_mmio_gpio_set(codec, 1, false);
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ca0113_mmio_gpio_set(codec, 7, true);
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ca0113_mmio_gpio_set(codec, 4, true);
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ca0113_mmio_gpio_set(codec, 1, false);
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chipio_set_control_param(codec, 0x0D, 0x12);
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break;
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case QUIRK_R3DI:
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@ -4064,7 +4131,7 @@ static int ca0132_alt_select_out(struct hda_codec *codec)
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break;
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case QUIRK_R3D:
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chipio_set_control_param(codec, 0x0D, 0x21);
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ca0132_mmio_gpio_set(codec, 0x1, false);
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ca0113_mmio_gpio_set(codec, 0x1, false);
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break;
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}
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@ -4099,9 +4166,9 @@ static int ca0132_alt_select_out(struct hda_codec *codec)
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/* Surround out config*/
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switch (spec->quirk) {
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case QUIRK_SBZ:
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ca0132_mmio_gpio_set(codec, 7, false);
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ca0132_mmio_gpio_set(codec, 4, true);
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ca0132_mmio_gpio_set(codec, 1, true);
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ca0113_mmio_gpio_set(codec, 7, false);
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ca0113_mmio_gpio_set(codec, 4, true);
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ca0113_mmio_gpio_set(codec, 1, true);
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chipio_set_control_param(codec, 0x0D, 0x18);
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break;
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case QUIRK_R3DI:
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@ -4109,7 +4176,7 @@ static int ca0132_alt_select_out(struct hda_codec *codec)
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r3di_gpio_out_set(codec, R3DI_LINE_OUT);
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break;
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case QUIRK_R3D:
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ca0132_mmio_gpio_set(codec, 1, true);
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ca0113_mmio_gpio_set(codec, 1, true);
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chipio_set_control_param(codec, 0x0D, 0x24);
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break;
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}
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@ -4370,7 +4437,7 @@ static int ca0132_alt_select_in(struct hda_codec *codec)
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switch (spec->quirk) {
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case QUIRK_SBZ:
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case QUIRK_R3D:
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ca0132_mmio_gpio_set(codec, 0, false);
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ca0113_mmio_gpio_set(codec, 0, false);
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tmp = FLOAT_THREE;
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break;
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case QUIRK_R3DI:
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@ -4403,7 +4470,7 @@ static int ca0132_alt_select_in(struct hda_codec *codec)
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switch (spec->quirk) {
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case QUIRK_SBZ:
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case QUIRK_R3D:
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ca0132_mmio_gpio_set(codec, 0, false);
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ca0113_mmio_gpio_set(codec, 0, false);
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break;
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case QUIRK_R3DI:
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r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
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@ -4430,8 +4497,8 @@ static int ca0132_alt_select_in(struct hda_codec *codec)
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switch (spec->quirk) {
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case QUIRK_SBZ:
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case QUIRK_R3D:
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ca0132_mmio_gpio_set(codec, 0, true);
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ca0132_mmio_gpio_set(codec, 5, false);
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ca0113_mmio_gpio_set(codec, 0, true);
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ca0113_mmio_gpio_set(codec, 5, false);
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tmp = FLOAT_THREE;
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break;
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case QUIRK_R3DI:
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@ -6977,11 +7044,11 @@ static void sbz_region2_exit(struct hda_codec *codec)
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for (i = 0; i < 8; i++)
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writeb(0xb3, spec->mem_base + 0x304);
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ca0132_mmio_gpio_set(codec, 0, false);
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ca0132_mmio_gpio_set(codec, 1, false);
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ca0132_mmio_gpio_set(codec, 4, true);
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ca0132_mmio_gpio_set(codec, 5, false);
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ca0132_mmio_gpio_set(codec, 7, false);
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ca0113_mmio_gpio_set(codec, 0, false);
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ca0113_mmio_gpio_set(codec, 1, false);
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ca0113_mmio_gpio_set(codec, 4, true);
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ca0113_mmio_gpio_set(codec, 5, false);
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ca0113_mmio_gpio_set(codec, 7, false);
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}
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static void sbz_set_pin_ctl_default(struct hda_codec *codec)
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@ -7291,6 +7358,47 @@ static void ca0132_mmio_init(struct hda_codec *codec)
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}
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}
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/*
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* This function writes to some SFR's, does some region2 writes, and then
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* eventually resets the codec with the 0x7ff verb. Not quite sure why it does
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* what it does.
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*/
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static void ae5_register_set(struct hda_codec *codec)
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{
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struct ca0132_spec *spec = codec->spec;
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chipio_8051_write_direct(codec, 0x93, 0x10);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
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writeb(0x0f, spec->mem_base + 0x304);
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writeb(0x0f, spec->mem_base + 0x304);
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writeb(0x0f, spec->mem_base + 0x304);
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writeb(0x0f, spec->mem_base + 0x304);
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writeb(0x0e, spec->mem_base + 0x100);
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writeb(0x1f, spec->mem_base + 0x304);
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writeb(0x0c, spec->mem_base + 0x100);
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writeb(0x3f, spec->mem_base + 0x304);
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writeb(0x08, spec->mem_base + 0x100);
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writeb(0x7f, spec->mem_base + 0x304);
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writeb(0x00, spec->mem_base + 0x100);
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writeb(0xff, spec->mem_base + 0x304);
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ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
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chipio_8051_write_direct(codec, 0x90, 0x00);
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chipio_8051_write_direct(codec, 0x90, 0x10);
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ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
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chipio_write(codec, 0x18b0a4, 0x000000c2);
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snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
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snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
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}
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/*
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* Extra init functions for alternative ca0132 codecs. Done
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* here so they don't clutter up the main ca0132_init function
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@ -7365,6 +7473,9 @@ static int ca0132_init(struct hda_codec *codec)
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snd_hda_power_up_pm(codec);
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if (spec->quirk == QUIRK_AE5)
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ae5_register_set(codec);
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ca0132_init_unsol(codec);
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ca0132_init_params(codec);
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ca0132_init_flags(codec);
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