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https://github.com/torvalds/linux
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Merge branches 'clk-fixed-rate', 'clk-spreadtrum', 'clk-pxa' and 'clk-ti' into clk-next
- More devm helpers for fixed rate registration - Add Spreadtrum UMS512 SoC clk support - Various PXA168 clk driver fixes * clk-fixed-rate: clk: fixed-rate: add devm_clk_hw_register_fixed_rate clk: asm9260: use parent index to link the reference clock * clk-spreadtrum: clk: sprd: Add clocks support for UMS512 * clk-pxa: clk: pxa: add a check for the return value of kzalloc() clk: mmp: pxa168: control shared SDH bits with separate clock dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks clk: mmp: pxa168: add clocks for SDH2 and SDH3 dt-bindings: marvell,pxa168: add clock id for SDH3 clk: mmp: pxa168: fix GPIO clock enable bits clk: mmp: pxa168: add muxes for more peripherals clk: mmp: pxa168: fix incorrect parent clocks clk: mmp: pxa168: fix const-correctness clk: mmp: pxa168: add new clocks for peripherals dt-bindings: marvell,pxa168: add clock ids for additional dividers clk: mmp: pxa168: fix incorrect dividers clk: mmp: pxa168: add additional register defines * clk-ti: clk: davinci: cfgchip: Use dev_err_probe() helper clk: davinci: pll: fix spelling typo in comment MAINTAINERS: add header file to TI DAVINCI SERIES CLOCK DRIVER
This commit is contained in:
Stephen Boyd
commit
b7f257ceb3
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@ -20308,6 +20308,7 @@ R: Sekhar Nori <nsekhar@ti.com>
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S: Maintained
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F: Documentation/devicetree/bindings/clock/ti/davinci/
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F: drivers/clk/davinci/
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F: include/linux/clk/davinci.h
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TI DAVINCI SERIES GPIO DRIVER
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M: Keerthy <j-keerthy@ti.com>
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@ -80,7 +80,7 @@ struct asm9260_mux_clock {
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u8 mask;
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u32 *table;
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const char *name;
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const char **parent_names;
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const struct clk_parent_data *parent_data;
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u8 num_parents;
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unsigned long offset;
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unsigned long flags;
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@ -232,10 +232,10 @@ static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = {
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HW_AHBCLKCTRL1, 16 },
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};
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static const char __initdata *main_mux_p[] = { NULL, NULL };
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static const char __initdata *i2s0_mux_p[] = { NULL, NULL, "i2s0m_div"};
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static const char __initdata *i2s1_mux_p[] = { NULL, NULL, "i2s1m_div"};
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static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"};
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static struct clk_parent_data __initdata main_mux_p[] = { { .index = 0, }, { .name = "pll" } };
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static struct clk_parent_data __initdata i2s0_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "i2s0m_div"} };
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static struct clk_parent_data __initdata i2s1_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "i2s1m_div"} };
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static struct clk_parent_data __initdata clkout_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "rtc"} };
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static u32 three_mux_table[] = {0, 1, 3};
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static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {
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@ -255,9 +255,10 @@ static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {
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static void __init asm9260_acc_init(struct device_node *np)
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{
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struct clk_hw *hw;
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struct clk_hw *hw, *pll_hw;
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struct clk_hw **hws;
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const char *ref_clk, *pll_clk = "pll";
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const char *pll_clk = "pll";
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struct clk_parent_data pll_parent_data = { .index = 0 };
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u32 rate;
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int n;
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@ -274,21 +275,15 @@ static void __init asm9260_acc_init(struct device_node *np)
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/* register pll */
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rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;
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/* TODO: Convert to DT parent scheme */
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ref_clk = of_clk_get_parent_name(np, 0);
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hw = __clk_hw_register_fixed_rate(NULL, NULL, pll_clk,
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ref_clk, NULL, NULL, 0, rate, 0,
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CLK_FIXED_RATE_PARENT_ACCURACY);
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if (IS_ERR(hw))
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pll_hw = clk_hw_register_fixed_rate_parent_accuracy(NULL, pll_clk, &pll_parent_data,
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0, rate);
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if (IS_ERR(pll_hw))
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panic("%pOFn: can't register REFCLK. Check DT!", np);
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for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {
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const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];
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mc->parent_names[0] = ref_clk;
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mc->parent_names[1] = pll_clk;
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hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names,
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hw = clk_hw_register_mux_table_parent_data(NULL, mc->name, mc->parent_data,
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mc->num_parents, mc->flags, base + mc->offset,
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0, mc->mask, 0, mc->table, &asm9260_clk_lock);
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}
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@ -49,12 +49,24 @@ const struct clk_ops clk_fixed_rate_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
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static void devm_clk_hw_register_fixed_rate_release(struct device *dev, void *res)
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{
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struct clk_fixed_rate *fix = res;
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/*
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* We can not use clk_hw_unregister_fixed_rate, since it will kfree()
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* the hw, resulting in double free. Just unregister the hw and let
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* devres code kfree() it.
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*/
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clk_hw_unregister(&fix->hw);
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}
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struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
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struct device_node *np, const char *name,
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const char *parent_name, const struct clk_hw *parent_hw,
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const struct clk_parent_data *parent_data, unsigned long flags,
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unsigned long fixed_rate, unsigned long fixed_accuracy,
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unsigned long clk_fixed_flags)
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unsigned long clk_fixed_flags, bool devm)
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{
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struct clk_fixed_rate *fixed;
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struct clk_hw *hw;
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@ -62,7 +74,11 @@ struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
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int ret = -EINVAL;
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/* allocate fixed-rate clock */
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fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
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if (devm)
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fixed = devres_alloc(devm_clk_hw_register_fixed_rate_release,
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sizeof(*fixed), GFP_KERNEL);
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else
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fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
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if (!fixed)
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return ERR_PTR(-ENOMEM);
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@ -90,9 +106,13 @@ struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
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else
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ret = of_clk_hw_register(np, hw);
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if (ret) {
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kfree(fixed);
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if (devm)
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devres_free(fixed);
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else
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kfree(fixed);
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hw = ERR_PTR(ret);
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}
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} else if (devm)
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devres_add(dev, fixed);
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return hw;
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}
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@ -510,8 +510,7 @@ da8xx_cfgchip_register_usb0_clk48(struct device *dev,
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fck_clk = devm_clk_get(dev, "fck");
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if (IS_ERR(fck_clk)) {
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if (PTR_ERR(fck_clk) != -EPROBE_DEFER)
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dev_err(dev, "Missing fck clock\n");
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dev_err_probe(dev, PTR_ERR(fck_clk), "Missing fck clock\n");
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return ERR_CAST(fck_clk);
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}
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@ -98,7 +98,7 @@
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* @hw: clk_hw for the pll
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* @base: Base memory address
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* @pllm_min: The minimum allowable PLLM[PLLM] value
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* @pllm_max: The maxiumum allowable PLLM[PLLM] value
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* @pllm_max: The maximum allowable PLLM[PLLM] value
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* @pllm_mask: Bitmask for PLLM[PLLM] value
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*/
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struct davinci_pll_clk {
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@ -19,9 +19,6 @@
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#include "clk.h"
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#include "reset.h"
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#define APBC_RTC 0x28
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#define APBC_TWSI0 0x2c
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#define APBC_KPC 0x30
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#define APBC_UART0 0x0
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#define APBC_UART1 0x4
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#define APBC_GPIO 0x8
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@ -29,20 +26,40 @@
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#define APBC_PWM1 0x10
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#define APBC_PWM2 0x14
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#define APBC_PWM3 0x18
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#define APBC_RTC 0x28
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#define APBC_TWSI0 0x2c
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#define APBC_KPC 0x30
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#define APBC_TIMER 0x34
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#define APBC_AIB 0x3c
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#define APBC_SW_JTAG 0x40
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#define APBC_ONEWIRE 0x48
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#define APBC_TWSI1 0x6c
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#define APBC_UART2 0x70
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#define APBC_AC97 0x84
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#define APBC_SSP0 0x81c
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#define APBC_SSP1 0x820
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#define APBC_SSP2 0x84c
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#define APBC_SSP3 0x858
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#define APBC_SSP4 0x85c
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#define APBC_TWSI1 0x6c
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#define APBC_UART2 0x70
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#define APMU_DISP0 0x4c
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#define APMU_CCIC0 0x50
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#define APMU_SDH0 0x54
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#define APMU_SDH1 0x58
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#define APMU_USB 0x5c
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#define APMU_DISP0 0x4c
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#define APMU_CCIC0 0x50
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#define APMU_DFC 0x60
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#define APMU_DMA 0x64
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#define APMU_BUS 0x6c
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#define APMU_GC 0xcc
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#define APMU_SMC 0xd4
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#define APMU_XD 0xdc
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#define APMU_SDH2 0xe0
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#define APMU_SDH3 0xe4
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#define APMU_CF 0xf0
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#define APMU_MSP 0xf4
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#define APMU_CMU 0xf8
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#define APMU_FE 0xfc
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#define APMU_PCIE 0x100
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#define APMU_EPD 0x104
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#define MPMU_UART_PLL 0x14
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struct pxa168_clk_unit {
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@ -71,9 +88,12 @@ static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
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{PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
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{PXA168_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
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{PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
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{PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
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{PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
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{PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 1, 5, 0},
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{PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 1, 5, 0},
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{PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
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{PXA168_CLK_PLL1_2_1_10, "pll1_2_1_10", "pll1_2", 1, 10, 0},
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{PXA168_CLK_PLL1_2_3_16, "pll1_2_3_16", "pll1_2", 3, 16, 0},
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{PXA168_CLK_CLK32_2, "clk32_2", "clk32", 1, 2, 0},
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};
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static struct mmp_clk_factor_masks uart_factor_masks = {
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@ -107,24 +127,44 @@ static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
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mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk);
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}
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static DEFINE_SPINLOCK(twsi0_lock);
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static DEFINE_SPINLOCK(twsi1_lock);
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static const char * const twsi_parent_names[] = {"pll1_2_1_10", "pll1_2_1_5"};
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static DEFINE_SPINLOCK(kpc_lock);
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static const char * const kpc_parent_names[] = {"clk32", "clk32_2", "pll1_24"};
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static DEFINE_SPINLOCK(pwm0_lock);
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static DEFINE_SPINLOCK(pwm1_lock);
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static DEFINE_SPINLOCK(pwm2_lock);
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static DEFINE_SPINLOCK(pwm3_lock);
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static const char * const pwm_parent_names[] = {"pll1_48", "clk32"};
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static DEFINE_SPINLOCK(uart0_lock);
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static DEFINE_SPINLOCK(uart1_lock);
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static DEFINE_SPINLOCK(uart2_lock);
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static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
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static const char * const uart_parent_names[] = {"pll1_2_3_16", "uart_pll"};
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static DEFINE_SPINLOCK(ssp0_lock);
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static DEFINE_SPINLOCK(ssp1_lock);
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static DEFINE_SPINLOCK(ssp2_lock);
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static DEFINE_SPINLOCK(ssp3_lock);
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static DEFINE_SPINLOCK(ssp4_lock);
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static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
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static const char * const ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
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static DEFINE_SPINLOCK(timer_lock);
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static const char *timer_parent_names[] = {"pll1_48", "clk32", "pll1_96", "pll1_192"};
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static const char * const timer_parent_names[] = {"pll1_48", "clk32", "pll1_96", "pll1_192"};
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static DEFINE_SPINLOCK(reset_lock);
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static struct mmp_param_mux_clk apbc_mux_clks[] = {
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{0, "twsi0_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0, 4, 3, 0, &twsi0_lock},
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{0, "twsi1_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI1, 4, 3, 0, &twsi1_lock},
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{0, "kpc_mux", kpc_parent_names, ARRAY_SIZE(kpc_parent_names), CLK_SET_RATE_PARENT, APBC_KPC, 4, 3, 0, &kpc_lock},
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{0, "pwm0_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4, 3, 0, &pwm0_lock},
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{0, "pwm1_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM1, 4, 3, 0, &pwm1_lock},
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{0, "pwm2_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM2, 4, 3, 0, &pwm2_lock},
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{0, "pwm3_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM3, 4, 3, 0, &pwm3_lock},
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{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
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{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
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{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
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@ -137,16 +177,15 @@ static struct mmp_param_mux_clk apbc_mux_clks[] = {
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};
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static struct mmp_param_gate_clk apbc_gate_clks[] = {
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{PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
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{PXA168_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
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{PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
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{PXA168_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
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{PXA168_CLK_TWSI0, "twsi0_clk", "twsi0_mux", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &twsi0_lock},
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{PXA168_CLK_TWSI1, "twsi1_clk", "twsi1_mux", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &twsi1_lock},
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{PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x1, 0x1, 0x0, 0, &reset_lock},
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{PXA168_CLK_KPC, "kpc_clk", "kpc_mux", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &kpc_lock},
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{PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
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{PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
|
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{PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
|
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{PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
|
||||
{PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
|
||||
/* The gate clocks has mux parent. */
|
||||
{PXA168_CLK_PWM0, "pwm0_clk", "pwm0_mux", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &pwm0_lock},
|
||||
{PXA168_CLK_PWM1, "pwm1_clk", "pwm1_mux", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &pwm1_lock},
|
||||
{PXA168_CLK_PWM2, "pwm2_clk", "pwm2_mux", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &pwm2_lock},
|
||||
{PXA168_CLK_PWM3, "pwm3_clk", "pwm3_mux", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &pwm3_lock},
|
||||
{PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
|
||||
{PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
|
||||
{PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
|
||||
|
|
@ -170,22 +209,30 @@ static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
|
|||
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(dfc_lock);
|
||||
static const char * const dfc_parent_names[] = {"pll1_4", "pll1_8"};
|
||||
|
||||
static DEFINE_SPINLOCK(sdh0_lock);
|
||||
static DEFINE_SPINLOCK(sdh1_lock);
|
||||
static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
|
||||
static DEFINE_SPINLOCK(sdh2_lock);
|
||||
static DEFINE_SPINLOCK(sdh3_lock);
|
||||
static const char * const sdh_parent_names[] = {"pll1_13", "pll1_12", "pll1_8"};
|
||||
|
||||
static DEFINE_SPINLOCK(usb_lock);
|
||||
|
||||
static DEFINE_SPINLOCK(disp0_lock);
|
||||
static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
|
||||
static const char * const disp_parent_names[] = {"pll1", "pll1_2"};
|
||||
|
||||
static DEFINE_SPINLOCK(ccic0_lock);
|
||||
static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
|
||||
static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
|
||||
static const char * const ccic_parent_names[] = {"pll1_4", "pll1_8"};
|
||||
static const char * const ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
|
||||
|
||||
static struct mmp_param_mux_clk apmu_mux_clks[] = {
|
||||
{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
|
||||
{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
|
||||
{0, "dfc_mux", dfc_parent_names, ARRAY_SIZE(dfc_parent_names), CLK_SET_RATE_PARENT, APMU_DFC, 6, 1, 0, &dfc_lock},
|
||||
{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 2, 0, &sdh0_lock},
|
||||
{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 2, 0, &sdh1_lock},
|
||||
{0, "sdh2_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH2, 6, 2, 0, &sdh2_lock},
|
||||
{0, "sdh3_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH3, 6, 2, 0, &sdh3_lock},
|
||||
{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
|
||||
{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
|
||||
{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
|
||||
|
|
@ -196,12 +243,16 @@ static struct mmp_param_div_clk apmu_div_clks[] = {
|
|||
};
|
||||
|
||||
static struct mmp_param_gate_clk apmu_gate_clks[] = {
|
||||
{PXA168_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
|
||||
{PXA168_CLK_DFC, "dfc_clk", "dfc_mux", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, &dfc_lock},
|
||||
{PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
|
||||
{PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
|
||||
/* The gate clocks has mux parent. */
|
||||
{PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
|
||||
{PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
|
||||
{PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock},
|
||||
{PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock},
|
||||
{PXA168_CLK_SDH2, "sdh2_clk", "sdh2_mux", CLK_SET_RATE_PARENT, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock},
|
||||
{PXA168_CLK_SDH3, "sdh3_clk", "sdh3_mux", CLK_SET_RATE_PARENT, APMU_SDH3, 0x12, 0x12, 0x0, 0, &sdh3_lock},
|
||||
/* SDH0/1 and 2/3 AXI clocks are also gated by common bits in SDH0 and SDH2 registers */
|
||||
{PXA168_CLK_SDH01_AXI, "sdh01_axi_clk", NULL, CLK_SET_RATE_PARENT, APMU_SDH0, 0x9, 0x9, 0x0, 0, &sdh0_lock},
|
||||
{PXA168_CLK_SDH23_AXI, "sdh23_axi_clk", NULL, CLK_SET_RATE_PARENT, APMU_SDH2, 0x9, 0x9, 0x0, 0, &sdh2_lock},
|
||||
{PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
|
||||
{PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
|
||||
{PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
|
||||
|
|
|
|||
|
|
@ -104,6 +104,8 @@ int __init clk_pxa_cken_init(const struct desc_clk_cken *clks,
|
|||
|
||||
for (i = 0; i < nb_clks; i++) {
|
||||
pxa_clk = kzalloc(sizeof(*pxa_clk), GFP_KERNEL);
|
||||
if (!pxa_clk)
|
||||
return -ENOMEM;
|
||||
pxa_clk->is_in_low_power = clks[i].is_in_low_power;
|
||||
pxa_clk->lp = clks[i].lp;
|
||||
pxa_clk->hp = clks[i].hp;
|
||||
|
|
|
|||
|
|
@ -21,4 +21,10 @@ config SPRD_SC9863A_CLK
|
|||
help
|
||||
Support for the global clock controller on sc9863a devices.
|
||||
Say Y if you want to use peripheral devices on sc9863a SoC.
|
||||
|
||||
config SPRD_UMS512_CLK
|
||||
tristate "Support for the Spreadtrum UMS512 clocks"
|
||||
help
|
||||
Support for the global clock controller on ums512 devices.
|
||||
Say Y if you want to use peripheral devices on ums512 SoC.
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -11,3 +11,4 @@ clk-sprd-y += pll.o
|
|||
## SoC support
|
||||
obj-$(CONFIG_SPRD_SC9860_CLK) += sc9860-clk.o
|
||||
obj-$(CONFIG_SPRD_SC9863A_CLK) += sc9863a-clk.o
|
||||
obj-$(CONFIG_SPRD_UMS512_CLK) += ums512-clk.o
|
||||
|
|
|
|||
2202
drivers/clk/sprd/ums512-clk.c
Normal file
2202
drivers/clk/sprd/ums512-clk.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -20,8 +20,11 @@
|
|||
#define PXA168_CLK_PLL1_2_1_5 19
|
||||
#define PXA168_CLK_PLL1_3_16 20
|
||||
#define PXA168_CLK_PLL1_192 21
|
||||
#define PXA168_CLK_PLL1_2_1_10 22
|
||||
#define PXA168_CLK_PLL1_2_3_16 23
|
||||
#define PXA168_CLK_UART_PLL 27
|
||||
#define PXA168_CLK_USB_PLL 28
|
||||
#define PXA168_CLK_CLK32_2 50
|
||||
|
||||
/* apb peripherals */
|
||||
#define PXA168_CLK_TWSI0 60
|
||||
|
|
@ -56,6 +59,9 @@
|
|||
#define PXA168_CLK_CCIC0 107
|
||||
#define PXA168_CLK_CCIC0_PHY 108
|
||||
#define PXA168_CLK_CCIC0_SPHY 109
|
||||
#define PXA168_CLK_SDH3 110
|
||||
#define PXA168_CLK_SDH01_AXI 111
|
||||
#define PXA168_CLK_SDH23_AXI 112
|
||||
|
||||
#define PXA168_NR_CLKS 200
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -350,7 +350,7 @@ struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
|
|||
const char *parent_name, const struct clk_hw *parent_hw,
|
||||
const struct clk_parent_data *parent_data, unsigned long flags,
|
||||
unsigned long fixed_rate, unsigned long fixed_accuracy,
|
||||
unsigned long clk_fixed_flags);
|
||||
unsigned long clk_fixed_flags, bool devm);
|
||||
struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
unsigned long fixed_rate);
|
||||
|
|
@ -365,7 +365,20 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
|||
*/
|
||||
#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (fixed_rate), 0, 0)
|
||||
NULL, (flags), (fixed_rate), 0, 0, false)
|
||||
|
||||
/**
|
||||
* devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
|
||||
* framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_name: name of clock's parent
|
||||
* @flags: framework-specific flags
|
||||
* @fixed_rate: non-adjustable clock rate
|
||||
*/
|
||||
#define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (fixed_rate), 0, 0, true)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
|
||||
* the clock framework
|
||||
|
|
@ -378,7 +391,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
|||
#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
|
||||
fixed_rate) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
|
||||
NULL, (flags), (fixed_rate), 0, 0)
|
||||
NULL, (flags), (fixed_rate), 0, 0, false)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
|
||||
* the clock framework
|
||||
|
|
@ -392,7 +405,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
|||
fixed_rate) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
|
||||
(parent_data), (flags), (fixed_rate), 0, \
|
||||
0)
|
||||
0, false)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
|
||||
* the clock framework
|
||||
|
|
@ -408,7 +421,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
|||
fixed_accuracy) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
|
||||
NULL, NULL, (flags), (fixed_rate), \
|
||||
(fixed_accuracy), 0)
|
||||
(fixed_accuracy), 0, false)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
|
||||
* clock with the clock framework
|
||||
|
|
@ -423,7 +436,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
|||
parent_hw, flags, fixed_rate, fixed_accuracy) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
|
||||
NULL, NULL, (flags), (fixed_rate), \
|
||||
(fixed_accuracy), 0)
|
||||
(fixed_accuracy), 0, false)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
|
||||
* clock with the clock framework
|
||||
|
|
@ -438,7 +451,21 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
|||
parent_data, flags, fixed_rate, fixed_accuracy) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
|
||||
(parent_data), NULL, (flags), \
|
||||
(fixed_rate), (fixed_accuracy), 0)
|
||||
(fixed_rate), (fixed_accuracy), 0, false)
|
||||
/**
|
||||
* clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
|
||||
* the clock framework
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_name: name of clock's parent
|
||||
* @flags: framework-specific flags
|
||||
* @fixed_rate: non-adjustable clock rate
|
||||
*/
|
||||
#define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
|
||||
flags, fixed_rate) \
|
||||
__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
|
||||
(parent_data), (flags), (fixed_rate), 0, \
|
||||
CLK_FIXED_RATE_PARENT_ACCURACY, false)
|
||||
|
||||
void clk_unregister_fixed_rate(struct clk *clk);
|
||||
void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
|
||||
|
|
@ -957,6 +984,13 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
|
|||
(parent_names), NULL, NULL, (flags), (reg), \
|
||||
(shift), (mask), (clk_mux_flags), (table), \
|
||||
(lock))
|
||||
#define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
|
||||
num_parents, flags, reg, shift, mask, \
|
||||
clk_mux_flags, table, lock) \
|
||||
__clk_hw_register_mux((dev), NULL, (name), (num_parents), \
|
||||
NULL, NULL, (parent_data), (flags), (reg), \
|
||||
(shift), (mask), (clk_mux_flags), (table), \
|
||||
(lock))
|
||||
#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
|
||||
shift, width, clk_mux_flags, lock) \
|
||||
__clk_hw_register_mux((dev), NULL, (name), (num_parents), \
|
||||
|
|
|
|||
Loading…
Reference in a new issue