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ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance

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There are two instances of PCIe PHY in DRA7xx. So renamed
optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to
optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk
respectively. This is needed for adding the clocks for second PCIe PHY
instance.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Kishon Vijay Abraham I 2014-07-14 16:12:19 +05:30 committed by Tony Lindgren
parent ba5137b272
commit b700f42c86
1 changed files with 3 additions and 3 deletions
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6
arch/arm/boot/dts/dra7xx-clocks.dtsi
View file

@ -1165,7 +1165,7 @@ apll_pcie_ck: apll_pcie_ck {
reg = <0x021c>, <0x0220>;
};
optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
@ -1183,7 +1183,7 @@ optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
ti,max-div = <2>;
};
optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
@ -1191,7 +1191,7 @@ optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
ti,bit-shift = <9>;
};
optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;