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phy: qcom-qmp-combo: use v6 registers in v6 regs layout

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Make sure that we use only v6 registers in qmp_v6_usb3phy_regs_layout.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230928105445.1210861-4-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2023-09-28 13:54:45 +03:00 committed by Vinod Koul
parent 5077b136fd
commit b5ec2824d7
3 changed files with 12 additions and 7 deletions
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12
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
View file

@ -194,14 +194,14 @@ static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
};
static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
[QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
[QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
[QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
/* In PCS_USB */
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
[QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL,
[QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS,

3
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
View file

@ -6,8 +6,9 @@
#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_
#define QCOM_PHY_QMP_PCS_USB_V6_H_
/* Only for QMP V6 PHY - USB3 have different offsets than V5 */
#define QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1 0x00
#define QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08
#define QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14
#define QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
#define QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
#define QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40

4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
View file

@ -7,6 +7,10 @@
#define QCOM_PHY_QMP_PCS_V6_H_
/* Only for QMP V6 PHY - USB/PCIe PCS registers */
#define QPHY_V6_PCS_SW_RESET 0x000
#define QPHY_V6_PCS_PCS_STATUS1 0x014
#define QPHY_V6_PCS_POWER_DOWN_CONTROL 0x040
#define QPHY_V6_PCS_START_CONTROL 0x044
#define QPHY_V6_PCS_POWER_STATE_CONFIG1 0x090
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG1 0x0c4
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG2 0x0c8