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Exynos 3250, 4415 drivers cleanup by using common code
and addition of clock definitions for DVFS on Exynos4. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCAAGBQJUyPwjAAoJEE1bIKeAnHqLbcQP/RQoZLdRJqhToiWxMKzQjaEh KPOAEBNGMOvPeVrf3Ct6r2a6elgLg6pKdYZcekupu9Vqrc0OXdHVKEM/YC7x5MEB Wzs/cuVZyYb8lhnWa0dmUTEQp/JvYX1Ifgp2xlKFc6ZPstuxIsp2HizQIS8+xsqW NxUIwkz1X0xyO4oLmVG7cO7co4FgSBfY3YI/PnUgDuixoX0X6eY0uNMLMS5J/5gP wOmwDmgJop/qi7tMfghDwDemF3/WJBY8V2D/dIvCoSsFu0bGAPqPnemEuaeBCbEo 1sVrvEz60kXaJSx7A44Or2KX8cvaSPExcVmG66idYLlOW+gGXgjCRZ11A2FmzBDb sWXMkwSNeZ3QxL6fmJuRkXYDbwHNWlKdZIjlM6+iYPjA78twUEN5tD1U1YTh0cy/ MCFmoUWJh2vpbQJiY3carcvq1NiNhALFUWrJK5zCoMybvIWrQhYBBCnZh7U1fDzo nmxLcDr1IG6eRjOfn6Q2XVmCXjhZX3kojAh/ePEHQGl5jyspZcMm4Top93sTO9l6 SBimh5wrafK8nTQN8NeNGNr3s3CfYVURu9GdEiJJwecHnWoeFFc/Y/w7qaWorNtM tsg7Gjk+95OgM+m8Cb8Nu8WXUyK7AYznbgldzypx7FVMQRpDW7/UjpB0lKjT7qeG c0ScBKIXZd6RNyzHM2TJ =rFdT -----END PGP SIGNATURE----- Merge tag 'v3.20-exynos-clk' of git://linuxtv.org/snawrocki/samsung into clk-next Exynos 3250, 4415 drivers cleanup by using common code and addition of clock definitions for DVFS on Exynos4.
This commit is contained in:
Michael Turquette
commit
b530e7d210
6 changed files with 118 additions and 348 deletions
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@ -104,27 +104,6 @@
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#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
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#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
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/* list of PLLs to be registered */
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enum exynos3250_plls {
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apll, mpll, vpll, upll,
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nr_plls
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};
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/* list of PLLs in DMC block to be registered */
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enum exynos3250_dmc_plls {
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bpll, epll,
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nr_dmc_plls
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};
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static void __iomem *reg_base;
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static void __iomem *dmc_reg_base;
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/*
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* Support for CMU save/restore across system suspends
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*/
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#ifdef CONFIG_PM_SLEEP
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static struct samsung_clk_reg_dump *exynos3250_clk_regs;
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static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
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SRC_LEFTBUS,
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DIV_LEFTBUS,
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@ -195,43 +174,6 @@ static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
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PWR_CTRL2,
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};
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static int exynos3250_clk_suspend(void)
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{
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samsung_clk_save(reg_base, exynos3250_clk_regs,
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ARRAY_SIZE(exynos3250_cmu_clk_regs));
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return 0;
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}
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static void exynos3250_clk_resume(void)
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{
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samsung_clk_restore(reg_base, exynos3250_clk_regs,
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ARRAY_SIZE(exynos3250_cmu_clk_regs));
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}
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static struct syscore_ops exynos3250_clk_syscore_ops = {
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.suspend = exynos3250_clk_suspend,
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.resume = exynos3250_clk_resume,
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};
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static void exynos3250_clk_sleep_init(void)
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{
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exynos3250_clk_regs =
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samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
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ARRAY_SIZE(exynos3250_cmu_clk_regs));
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if (!exynos3250_clk_regs) {
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pr_warn("%s: Failed to allocate sleep save data\n", __func__);
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goto err;
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}
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register_syscore_ops(&exynos3250_clk_syscore_ops);
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return;
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err:
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kfree(exynos3250_clk_regs);
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}
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#else
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static inline void exynos3250_clk_sleep_init(void) { }
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#endif
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/* list of all parent clock list */
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PNAME(mout_vpllsrc_p) = { "fin_pll", };
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@ -782,18 +724,18 @@ static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
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{ /* sentinel */ }
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};
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static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
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[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
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APLL_LOCK, APLL_CON0, NULL),
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[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
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MPLL_LOCK, MPLL_CON0, NULL),
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[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
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VPLL_LOCK, VPLL_CON0, NULL),
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[upll] = PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
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UPLL_LOCK, UPLL_CON0, NULL),
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static struct samsung_pll_clock exynos3250_plls[] __initdata = {
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PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
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APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
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PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
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MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates),
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PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
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VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates),
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PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
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UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
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};
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static void __init exynos3_core_down_clock(void)
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static void __init exynos3_core_down_clock(void __iomem *reg_base)
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{
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unsigned int tmp;
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@ -814,38 +756,31 @@ static void __init exynos3_core_down_clock(void)
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__raw_writel(0x0, reg_base + PWR_CTRL2);
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}
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static struct samsung_cmu_info cmu_info __initdata = {
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.pll_clks = exynos3250_plls,
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.nr_pll_clks = ARRAY_SIZE(exynos3250_plls),
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.mux_clks = mux_clks,
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.nr_mux_clks = ARRAY_SIZE(mux_clks),
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.div_clks = div_clks,
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.nr_div_clks = ARRAY_SIZE(div_clks),
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.gate_clks = gate_clks,
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.nr_gate_clks = ARRAY_SIZE(gate_clks),
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.fixed_factor_clks = fixed_factor_clks,
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.nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
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.nr_clk_ids = CLK_NR_CLKS,
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.clk_regs = exynos3250_cmu_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
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};
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static void __init exynos3250_cmu_init(struct device_node *np)
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{
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struct samsung_clk_provider *ctx;
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reg_base = of_iomap(np, 0);
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if (!reg_base)
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panic("%s: failed to map registers\n", __func__);
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ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
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ctx = samsung_cmu_register_one(np, &cmu_info);
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if (!ctx)
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panic("%s: unable to allocate context.\n", __func__);
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return;
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samsung_clk_register_fixed_factor(ctx, fixed_factor_clks,
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ARRAY_SIZE(fixed_factor_clks));
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exynos3250_plls[apll].rate_table = exynos3250_pll_rates;
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exynos3250_plls[mpll].rate_table = exynos3250_pll_rates;
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exynos3250_plls[vpll].rate_table = exynos3250_vpll_rates;
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exynos3250_plls[upll].rate_table = exynos3250_pll_rates;
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samsung_clk_register_pll(ctx, exynos3250_plls,
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ARRAY_SIZE(exynos3250_plls), reg_base);
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samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
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samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
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samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
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exynos3_core_down_clock();
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exynos3250_clk_sleep_init();
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samsung_clk_of_add_provider(np, ctx);
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exynos3_core_down_clock(ctx->reg_base);
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}
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CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
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@ -872,12 +807,6 @@ CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
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#define EPLL_CON2 0x111c
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#define SRC_EPLL 0x1120
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/*
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* Support for CMU save/restore across system suspends
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*/
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#ifdef CONFIG_PM_SLEEP
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static struct samsung_clk_reg_dump *exynos3250_dmc_clk_regs;
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static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = {
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BPLL_LOCK,
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BPLL_CON0,
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@ -899,43 +828,6 @@ static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = {
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SRC_EPLL,
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};
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static int exynos3250_dmc_clk_suspend(void)
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{
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samsung_clk_save(dmc_reg_base, exynos3250_dmc_clk_regs,
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ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
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return 0;
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}
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static void exynos3250_dmc_clk_resume(void)
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{
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samsung_clk_restore(dmc_reg_base, exynos3250_dmc_clk_regs,
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ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
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}
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static struct syscore_ops exynos3250_dmc_clk_syscore_ops = {
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.suspend = exynos3250_dmc_clk_suspend,
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.resume = exynos3250_dmc_clk_resume,
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};
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static void exynos3250_dmc_clk_sleep_init(void)
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{
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exynos3250_dmc_clk_regs =
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samsung_clk_alloc_reg_dump(exynos3250_cmu_dmc_clk_regs,
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ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
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if (!exynos3250_dmc_clk_regs) {
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pr_warn("%s: Failed to allocate sleep save data\n", __func__);
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goto err;
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}
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register_syscore_ops(&exynos3250_dmc_clk_syscore_ops);
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return;
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err:
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kfree(exynos3250_dmc_clk_regs);
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}
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#else
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static inline void exynos3250_dmc_clk_sleep_init(void) { }
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#endif
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PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
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PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
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PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", };
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@ -977,43 +869,28 @@ static struct samsung_div_clock dmc_div_clks[] __initdata = {
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DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
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};
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static struct samsung_pll_clock exynos3250_dmc_plls[nr_dmc_plls] __initdata = {
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[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
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BPLL_LOCK, BPLL_CON0, NULL),
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[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
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EPLL_LOCK, EPLL_CON0, NULL),
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static struct samsung_pll_clock exynos3250_dmc_plls[] __initdata = {
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PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
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BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),
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PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
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EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),
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};
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static struct samsung_cmu_info dmc_cmu_info __initdata = {
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.pll_clks = exynos3250_dmc_plls,
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.nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls),
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.mux_clks = dmc_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
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.div_clks = dmc_div_clks,
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.nr_div_clks = ARRAY_SIZE(dmc_div_clks),
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.nr_clk_ids = NR_CLKS_DMC,
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.clk_regs = exynos3250_cmu_dmc_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
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};
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static void __init exynos3250_cmu_dmc_init(struct device_node *np)
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{
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struct samsung_clk_provider *ctx;
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dmc_reg_base = of_iomap(np, 0);
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if (!dmc_reg_base)
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panic("%s: failed to map registers\n", __func__);
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ctx = samsung_clk_init(np, dmc_reg_base, NR_CLKS_DMC);
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if (!ctx)
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panic("%s: unable to allocate context.\n", __func__);
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exynos3250_dmc_plls[bpll].rate_table = exynos3250_pll_rates;
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exynos3250_dmc_plls[epll].rate_table = exynos3250_epll_rates;
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pr_err("CLK registering epll bpll: %d, %d, %d, %d\n",
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exynos3250_dmc_plls[bpll].rate_table[0].rate,
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exynos3250_dmc_plls[bpll].rate_table[0].mdiv,
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exynos3250_dmc_plls[bpll].rate_table[0].pdiv,
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exynos3250_dmc_plls[bpll].rate_table[0].sdiv
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);
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samsung_clk_register_pll(ctx, exynos3250_dmc_plls,
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ARRAY_SIZE(exynos3250_dmc_plls), dmc_reg_base);
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samsung_clk_register_mux(ctx, dmc_mux_clks, ARRAY_SIZE(dmc_mux_clks));
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samsung_clk_register_div(ctx, dmc_div_clks, ARRAY_SIZE(dmc_div_clks));
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exynos3250_dmc_clk_sleep_init();
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samsung_clk_of_add_provider(np, ctx);
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samsung_cmu_register_one(np, &dmc_cmu_info);
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}
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CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
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exynos3250_cmu_dmc_init);
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@ -703,12 +703,12 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
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/* list of divider clocks supported in all exynos4 soc's */
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static struct samsung_div_clock exynos4_div_clks[] __initdata = {
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DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
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DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
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DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
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DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
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CLKOUT_CMU_LEFTBUS, 8, 6),
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DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
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DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
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DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
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DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
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CLKOUT_CMU_RIGHTBUS, 8, 6),
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@ -781,10 +781,10 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
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CLK_SET_RATE_PARENT, 0),
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DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
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DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
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DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
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DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
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DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
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DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
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DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
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DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
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DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
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DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
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@ -829,7 +829,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
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DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
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8, 3, CLK_GET_RATE_NOCACHE, 0),
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DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
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DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
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DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
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DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
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};
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@ -113,19 +113,6 @@
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#define DIV_CPU0 0x14500
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#define DIV_CPU1 0x14504
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enum exynos4415_plls {
|
||||
apll, epll, g3d_pll, isp_pll, disp_pll,
|
||||
nr_plls,
|
||||
};
|
||||
|
||||
static struct samsung_clk_provider *exynos4415_ctx;
|
||||
|
||||
/*
|
||||
* Support for CMU save/restore across system suspends
|
||||
*/
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *exynos4415_clk_regs;
|
||||
|
||||
static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
|
||||
SRC_LEFTBUS,
|
||||
DIV_LEFTBUS,
|
||||
|
|
@ -219,41 +206,6 @@ static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
|
|||
DIV_CPU1,
|
||||
};
|
||||
|
||||
static int exynos4415_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs,
|
||||
ARRAY_SIZE(exynos4415_cmu_clk_regs));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4415_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs,
|
||||
ARRAY_SIZE(exynos4415_cmu_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops exynos4415_clk_syscore_ops = {
|
||||
.suspend = exynos4415_clk_suspend,
|
||||
.resume = exynos4415_clk_resume,
|
||||
};
|
||||
|
||||
static void exynos4415_clk_sleep_init(void)
|
||||
{
|
||||
exynos4415_clk_regs =
|
||||
samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs,
|
||||
ARRAY_SIZE(exynos4415_cmu_clk_regs));
|
||||
if (!exynos4415_clk_regs) {
|
||||
pr_warn("%s: Failed to allocate sleep save data\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
register_syscore_ops(&exynos4415_clk_syscore_ops);
|
||||
}
|
||||
#else
|
||||
static inline void exynos4415_clk_sleep_init(void) { }
|
||||
#endif
|
||||
|
||||
/* list of all parent clock list */
|
||||
PNAME(mout_g3d_pllsrc_p) = { "fin_pll", };
|
||||
|
||||
|
|
@ -959,56 +911,40 @@ static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
|
|||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = {
|
||||
[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
|
||||
APLL_LOCK, APLL_CON0, NULL),
|
||||
[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
|
||||
EPLL_LOCK, EPLL_CON0, NULL),
|
||||
[g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll",
|
||||
"mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL),
|
||||
[isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
|
||||
ISP_PLL_LOCK, ISP_PLL_CON0, NULL),
|
||||
[disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
|
||||
"fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL),
|
||||
static struct samsung_pll_clock exynos4415_plls[] __initdata = {
|
||||
PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
|
||||
APLL_LOCK, APLL_CON0, exynos4415_pll_rates),
|
||||
PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
|
||||
EPLL_LOCK, EPLL_CON0, exynos4415_epll_rates),
|
||||
PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "mout_g3d_pllsrc",
|
||||
G3D_PLL_LOCK, G3D_PLL_CON0, exynos4415_pll_rates),
|
||||
PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
|
||||
ISP_PLL_LOCK, ISP_PLL_CON0, exynos4415_pll_rates),
|
||||
PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
|
||||
"fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info cmu_info __initdata = {
|
||||
.pll_clks = exynos4415_plls,
|
||||
.nr_pll_clks = ARRAY_SIZE(exynos4415_plls),
|
||||
.mux_clks = exynos4415_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(exynos4415_mux_clks),
|
||||
.div_clks = exynos4415_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(exynos4415_div_clks),
|
||||
.gate_clks = exynos4415_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(exynos4415_gate_clks),
|
||||
.fixed_clks = exynos4415_fixed_rate_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(exynos4415_fixed_rate_clks),
|
||||
.fixed_factor_clks = exynos4415_fixed_factor_clks,
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(exynos4415_fixed_factor_clks),
|
||||
.nr_clk_ids = CLK_NR_CLKS,
|
||||
.clk_regs = exynos4415_cmu_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos4415_cmu_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
|
||||
exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
if (!exynos4415_ctx)
|
||||
panic("%s: unable to allocate context.\n", __func__);
|
||||
|
||||
exynos4415_plls[apll].rate_table = exynos4415_pll_rates;
|
||||
exynos4415_plls[epll].rate_table = exynos4415_epll_rates;
|
||||
exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates;
|
||||
exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates;
|
||||
exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates;
|
||||
|
||||
samsung_clk_register_fixed_factor(exynos4415_ctx,
|
||||
exynos4415_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos4415_fixed_factor_clks));
|
||||
samsung_clk_register_fixed_rate(exynos4415_ctx,
|
||||
exynos4415_fixed_rate_clks,
|
||||
ARRAY_SIZE(exynos4415_fixed_rate_clks));
|
||||
|
||||
samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls,
|
||||
ARRAY_SIZE(exynos4415_plls), reg_base);
|
||||
samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks,
|
||||
ARRAY_SIZE(exynos4415_mux_clks));
|
||||
samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks,
|
||||
ARRAY_SIZE(exynos4415_div_clks));
|
||||
samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks,
|
||||
ARRAY_SIZE(exynos4415_gate_clks));
|
||||
|
||||
exynos4415_clk_sleep_init();
|
||||
|
||||
samsung_clk_of_add_provider(np, exynos4415_ctx);
|
||||
samsung_cmu_register_one(np, &cmu_info);
|
||||
}
|
||||
CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
|
||||
|
||||
|
|
@ -1027,16 +963,6 @@ CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
|
|||
#define SRC_DMC 0x300
|
||||
#define DIV_DMC1 0x504
|
||||
|
||||
enum exynos4415_dmc_plls {
|
||||
mpll, bpll,
|
||||
nr_dmc_plls,
|
||||
};
|
||||
|
||||
static struct samsung_clk_provider *exynos4415_dmc_ctx;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs;
|
||||
|
||||
static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
|
||||
MPLL_LOCK,
|
||||
MPLL_CON0,
|
||||
|
|
@ -1050,42 +976,6 @@ static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
|
|||
DIV_DMC1,
|
||||
};
|
||||
|
||||
static int exynos4415_dmc_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(exynos4415_dmc_ctx->reg_base,
|
||||
exynos4415_dmc_clk_regs,
|
||||
ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4415_dmc_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(exynos4415_dmc_ctx->reg_base,
|
||||
exynos4415_dmc_clk_regs,
|
||||
ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops exynos4415_dmc_clk_syscore_ops = {
|
||||
.suspend = exynos4415_dmc_clk_suspend,
|
||||
.resume = exynos4415_dmc_clk_resume,
|
||||
};
|
||||
|
||||
static void exynos4415_dmc_clk_sleep_init(void)
|
||||
{
|
||||
exynos4415_dmc_clk_regs =
|
||||
samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs,
|
||||
ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
|
||||
if (!exynos4415_dmc_clk_regs) {
|
||||
pr_warn("%s: Failed to allocate sleep save data\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
register_syscore_ops(&exynos4415_dmc_clk_syscore_ops);
|
||||
}
|
||||
#else
|
||||
static inline void exynos4415_dmc_clk_sleep_init(void) { }
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
|
||||
PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
|
||||
PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", };
|
||||
|
|
@ -1107,38 +997,28 @@ static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
|
|||
DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
|
||||
};
|
||||
|
||||
static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = {
|
||||
[mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
|
||||
MPLL_LOCK, MPLL_CON0, NULL),
|
||||
[bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
|
||||
BPLL_LOCK, BPLL_CON0, NULL),
|
||||
static struct samsung_pll_clock exynos4415_dmc_plls[] __initdata = {
|
||||
PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
|
||||
MPLL_LOCK, MPLL_CON0, exynos4415_pll_rates),
|
||||
PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
|
||||
BPLL_LOCK, BPLL_CON0, exynos4415_pll_rates),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info cmu_dmc_info __initdata = {
|
||||
.pll_clks = exynos4415_dmc_plls,
|
||||
.nr_pll_clks = ARRAY_SIZE(exynos4415_dmc_plls),
|
||||
.mux_clks = exynos4415_dmc_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(exynos4415_dmc_mux_clks),
|
||||
.div_clks = exynos4415_dmc_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(exynos4415_dmc_div_clks),
|
||||
.nr_clk_ids = NR_CLKS_DMC,
|
||||
.clk_regs = exynos4415_cmu_dmc_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos4415_cmu_dmc_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
|
||||
exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC);
|
||||
if (!exynos4415_dmc_ctx)
|
||||
panic("%s: unable to allocate context.\n", __func__);
|
||||
|
||||
exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates;
|
||||
exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates;
|
||||
|
||||
samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls,
|
||||
ARRAY_SIZE(exynos4415_dmc_plls), reg_base);
|
||||
samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks,
|
||||
ARRAY_SIZE(exynos4415_dmc_mux_clks));
|
||||
samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks,
|
||||
ARRAY_SIZE(exynos4415_dmc_div_clks));
|
||||
|
||||
exynos4415_dmc_clk_sleep_init();
|
||||
|
||||
samsung_clk_of_add_provider(np, exynos4415_dmc_ctx);
|
||||
samsung_cmu_register_one(np, &cmu_dmc_info);
|
||||
}
|
||||
CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
|
||||
exynos4415_cmu_dmc_init);
|
||||
|
|
|
|||
|
|
@ -374,19 +374,24 @@ static void samsung_clk_sleep_init(void __iomem *reg_base,
|
|||
* Common function which registers plls, muxes, dividers and gates
|
||||
* for each CMU. It also add CMU register list to register cache.
|
||||
*/
|
||||
void __init samsung_cmu_register_one(struct device_node *np,
|
||||
struct samsung_clk_provider * __init samsung_cmu_register_one(
|
||||
struct device_node *np,
|
||||
struct samsung_cmu_info *cmu)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct samsung_clk_provider *ctx;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
if (!reg_base) {
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
|
||||
if (!ctx)
|
||||
if (!ctx) {
|
||||
panic("%s: unable to alllocate ctx\n", __func__);
|
||||
return ctx;
|
||||
}
|
||||
|
||||
if (cmu->pll_clks)
|
||||
samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
|
||||
|
|
@ -410,4 +415,6 @@ void __init samsung_cmu_register_one(struct device_node *np,
|
|||
cmu->nr_clk_regs);
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
return ctx;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -392,7 +392,8 @@ extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
|||
struct samsung_pll_clock *pll_list,
|
||||
unsigned int nr_clk, void __iomem *base);
|
||||
|
||||
extern void __init samsung_cmu_register_one(struct device_node *,
|
||||
extern struct samsung_clk_provider __init *samsung_cmu_register_one(
|
||||
struct device_node *,
|
||||
struct samsung_cmu_info *);
|
||||
|
||||
extern unsigned long _get_rate(const char *clk_name);
|
||||
|
|
|
|||
|
|
@ -262,8 +262,13 @@
|
|||
#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ACP 456
|
||||
#define CLK_DIV_DMC 457
|
||||
#define CLK_DIV_C2C 458 /* Exynos4x12 only */
|
||||
#define CLK_DIV_GDL 459
|
||||
#define CLK_DIV_GDR 460
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 456
|
||||
#define CLK_NR_CLKS 461
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue