Meson Clock fixes:

- mpll: fix mpll0 fractional part ignored
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJZgHG0AAoJEHfc29rIyEnRKCwQAIoujlfO+NULaxl7JgGagZDy
 nJ1FU1kShDtm/pgWbW52cC92zgCJl5PGihxnwPVdJWd59TNKjPoREr1m5S8mWXPv
 IOVVoDg5VRfLVhwcuETi0aiXUmFjRQusgjM9NXyZpTcx2MtPY2CB92OMoaiITJgm
 a85tsfpptCQqAfixYsp8IqiHMnbLRj2Ntbf5+bHTcHrUnLmUUIJh6Fa7+16f8KJo
 JaYQ95X1c1ems4ECrYFINCgfNpi659deIum/UPZKysX0f8c78k0ANV9sMAyBazs8
 dhEdOWaGAohzyGJZg+btXLLnaRNGqVExP8qZ2X3+11Ob9r3VS95+sN7X19x+4q7C
 jKxgreD4jR3vv5ayXv/H15GK/y6xdDyO7vTkiMA9km8o5FK1Q/NYAlEbJx0Sr/v6
 Z3Dvp1IDdTNCzVa4ASmAyqOTOsx8SSqp6CdlpoQrutSrbnQsVZ8hleYrxjrGbsKC
 StB1g9JQEqOurOzMd50CdreKghCtQeI3TegxEKmhm++Q9sBD7KVhOpPw9ccty181
 GaEdfcdscKouT90c4tog3EwFihjoi2oidlU9PioJTIfeBfAE7q8P4ozMjzP7DCVd
 rSg9thk20oZYnep9UHF0NzM8JXv1dKcPTw44dkGRtj4JL9F0Grv8xFwgvXHG9SMU
 sRcgc13O8rNF6jjUQeJn
 =sv+n
 -----END PGP SIGNATURE-----

Merge tag 'meson-clk-fixes-for-4.13-rc4-v2' of git://github.com/baylibre/clk-meson into clk-fixes

Pull one Meson clock fix from Neil Armstrong

* tag 'meson-clk-fixes-for-4.13-rc4-v2' of git://github.com/baylibre/clk-meson:
  clk: meson: mpll: fix mpll0 fractional part ignored

drivers/clk/meson/clk-mpll.c

@@ -161,6 +161,13 @@ static int mpll_set_rate(struct clk_hw *hw,
 	reg = PARM_SET(p->width, p->shift, reg, 1);
 	writel(reg, mpll->base + p->reg_off);
 
+	p = &mpll->ssen;
+	if (p->width != 0) {
+		reg = readl(mpll->base + p->reg_off);
+		reg = PARM_SET(p->width, p->shift, reg, 1);
+		writel(reg, mpll->base + p->reg_off);
+	}
+
 	p = &mpll->n2;
 	reg = readl(mpll->base + p->reg_off);
 	reg = PARM_SET(p->width, p->shift, reg, n2);

drivers/clk/meson/clkc.h

@@ -118,6 +118,7 @@ struct meson_clk_mpll {
 	struct parm sdm_en;
 	struct parm n2;
 	struct parm en;
+	struct parm ssen;
 	spinlock_t *lock;
 };
 

drivers/clk/meson/gxbb.c

@@ -528,6 +528,11 @@ static struct meson_clk_mpll gxbb_mpll0 = {
 		.shift   = 14,
 		.width	 = 1,
 	},
+	.ssen = {
+		.reg_off = HHI_MPLL_CNTL,
+		.shift   = 25,
+		.width	 = 1,
+	},
 	.lock = &clk_lock,
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0",

drivers/clk/meson/meson8b.c

@@ -267,6 +267,11 @@ static struct meson_clk_mpll meson8b_mpll0 = {
 		.shift   = 14,
 		.width   = 1,
 	},
+	.ssen = {
+		.reg_off = HHI_MPLL_CNTL,
+		.shift   = 25,
+		.width   = 1,
+	},
 	.lock = &clk_lock,
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0",