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ath6kl: Fix endianness in requesting chip register read
Need to make sure the chip address for which we need the value si endian safe. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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@ -178,8 +178,8 @@ void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie)
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static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr)
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{
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int status;
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u8 addr_val[4];
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s32 i;
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__le32 addr_val;
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/*
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* Write bytes 1,2,3 of the register to set the upper address bytes,
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@ -189,16 +189,18 @@ static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr)
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for (i = 1; i <= 3; i++) {
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/*
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* Fill the buffer with the address byte value we want to
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* hit 4 times.
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* hit 4 times. No need to worry about endianness as the
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* same byte is copied to all four bytes of addr_val at
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* any time.
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*/
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memset(addr_val, ((u8 *)&addr)[i], 4);
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memset((u8 *)&addr_val, ((u8 *)&addr)[i], 4);
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/*
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* Hit each byte of the register address with a 4-byte
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* write operation to the same address, this is a harmless
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* operation.
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*/
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status = hif_read_write_sync(ar, reg_addr + i, addr_val,
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status = hif_read_write_sync(ar, reg_addr + i, (u8 *)&addr_val,
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4, HIF_WR_SYNC_BYTE_FIX);
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if (status)
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break;
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@ -216,7 +218,9 @@ static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr)
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* cycle to start, the extra 3 byte write to bytes 1,2,3 has no
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* effect since we are writing the same values again
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*/
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status = hif_read_write_sync(ar, reg_addr, (u8 *)(&addr),
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addr_val = cpu_to_le32(addr);
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status = hif_read_write_sync(ar, reg_addr,
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(u8 *)&(addr_val),
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4, HIF_WR_SYNC_BYTE_INC);
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if (status) {
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