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omap4: l2x0: Set share override bit
Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -80,6 +80,7 @@ static int __init omap_l2_cache_init(void)
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aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
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} else {
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aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
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(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
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(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
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(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT));
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}
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