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arm: zynq: timer: Remove unnecessary register write

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Acknowedging an interrupt requires to read the interrupt register
only. The write was only required to work around a bug in
the QEMU implementation of the TTC, which is fixed.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>
This commit is contained in:
Soren Brinkmann 2012-12-19 10:18:37 -08:00 committed by Michal Simek
parent f184c5caa9
commit af7f032dba
1 changed files with 1 additions and 2 deletions
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3
arch/arm/mach-zynq/timer.c
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@ -121,8 +121,7 @@ static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
struct xttcps_timer *timer = &xttce->xttc;
/* Acknowledge the interrupt and call event handler */
__raw_writel(__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET),
timer->base_addr + XTTCPS_ISR_OFFSET);
__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
xttce->ce.event_handler(&xttce->ce);