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MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

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Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.

Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
This commit is contained in:
Florian Fainelli 2014-01-14 09:54:40 -08:00 committed by Ralf Baechle
parent a4c0201e23
commit af2418be63
1 changed files with 1 additions and 0 deletions
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arch/mips/Kconfig
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@ -138,6 +138,7 @@ config BCM63XX
select SWAP_IO_SPACE
select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK
select MIPS_L1_CACHE_SHIFT_4
help
Support for BCM63XX based boards