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crypto: hisilicon/sec - add the register configuration for HW V3
Added the register configuration of the SVA mode for HW V3. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -90,6 +90,10 @@
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SEC_USER1_WB_DATA_SSV)
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SEC_USER1_WB_DATA_SSV)
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#define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET)
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#define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET)
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#define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET)
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#define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET)
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#define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220
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#define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224
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#define SEC_USER1_SMMU_NORMAL_V3 (BIT(23) | BIT(17) | BIT(11) | BIT(5))
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#define SEC_USER1_SMMU_MASK_V3 0xFF79E79E
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#define SEC_CORE_INT_STATUS_M_ECC BIT(2)
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#define SEC_CORE_INT_STATUS_M_ECC BIT(2)
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#define SEC_PREFETCH_CFG 0x301130
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#define SEC_PREFETCH_CFG 0x301130
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@ -335,6 +339,41 @@ static void sec_set_endian(struct hisi_qm *qm)
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writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
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writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
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}
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}
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static void sec_engine_sva_config(struct hisi_qm *qm)
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{
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u32 reg;
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if (qm->ver > QM_HW_V2) {
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reg = readl_relaxed(qm->io_base +
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SEC_INTERFACE_USER_CTRL0_REG_V3);
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reg |= SEC_USER0_SMMU_NORMAL;
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writel_relaxed(reg, qm->io_base +
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SEC_INTERFACE_USER_CTRL0_REG_V3);
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reg = readl_relaxed(qm->io_base +
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SEC_INTERFACE_USER_CTRL1_REG_V3);
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reg &= SEC_USER1_SMMU_MASK_V3;
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reg |= SEC_USER1_SMMU_NORMAL_V3;
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writel_relaxed(reg, qm->io_base +
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SEC_INTERFACE_USER_CTRL1_REG_V3);
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} else {
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reg = readl_relaxed(qm->io_base +
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SEC_INTERFACE_USER_CTRL0_REG);
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reg |= SEC_USER0_SMMU_NORMAL;
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writel_relaxed(reg, qm->io_base +
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SEC_INTERFACE_USER_CTRL0_REG);
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reg = readl_relaxed(qm->io_base +
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SEC_INTERFACE_USER_CTRL1_REG);
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reg &= SEC_USER1_SMMU_MASK;
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if (qm->use_sva)
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reg |= SEC_USER1_SMMU_SVA;
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else
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reg |= SEC_USER1_SMMU_NORMAL;
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writel_relaxed(reg, qm->io_base +
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SEC_INTERFACE_USER_CTRL1_REG);
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}
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}
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static void sec_open_sva_prefetch(struct hisi_qm *qm)
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static void sec_open_sva_prefetch(struct hisi_qm *qm)
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{
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{
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u32 val;
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u32 val;
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@ -426,17 +465,7 @@ static int sec_engine_init(struct hisi_qm *qm)
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reg |= (0x1 << SEC_TRNG_EN_SHIFT);
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reg |= (0x1 << SEC_TRNG_EN_SHIFT);
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writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
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writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
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reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL0_REG);
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sec_engine_sva_config(qm);
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reg |= SEC_USER0_SMMU_NORMAL;
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writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL0_REG);
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reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL1_REG);
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reg &= SEC_USER1_SMMU_MASK;
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if (qm->use_sva && qm->ver == QM_HW_V2)
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reg |= SEC_USER1_SMMU_SVA;
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else
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reg |= SEC_USER1_SMMU_NORMAL;
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writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL1_REG);
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writel(SEC_SINGLE_PORT_MAX_TRANS,
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writel(SEC_SINGLE_PORT_MAX_TRANS,
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qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);
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qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);
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