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bpf, docs: Document BPF insn encoding in term of stored bytes
[Changes from V4: - s/regs:16/regs:8 in figure.] [Changes from V3: - Back to src_reg and dst_reg, since they denote register numbers as opposed to the values stored in these registers.] [Changes from V2: - Use src and dst consistently in the document. - Use a more graphical depiction of the 128-bit instruction. - Remove `Where:' fragment. - Clarify that unused bits are reserved and shall be zeroed.] [Changes from V1: - Use rst literal blocks for figures. - Avoid using | in the basic instruction/pseudo instruction figure. - Rebased to today's bpf-next master branch.] This patch modifies instruction-set.rst so it documents the encoding of BPF instructions in terms of how the bytes are stored (be it in an ELF file or as bytes in a memory buffer to be loaded into the kernel or some other BPF consumer) as opposed to how the instruction looks like once loaded. This is hopefully easier to understand by implementors looking to generate and/or consume bytes conforming BPF instructions. The patch also clarifies that the unused bytes in a pseudo-instruction shall be cleared with zeros. Signed-off-by: Jose E. Marchesi <jose.marchesi@oracle.com> Acked-by: Yonghong Song <yhs@fb.com> Acked-by: David Vernet <void@manifault.com> Link: https://lore.kernel.org/r/87h6v6i0da.fsf_-_@oracle.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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@ -38,15 +38,11 @@ eBPF has two instruction encodings:
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* the wide instruction encoding, which appends a second 64-bit immediate (i.e.,
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* the wide instruction encoding, which appends a second 64-bit immediate (i.e.,
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constant) value after the basic instruction for a total of 128 bits.
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constant) value after the basic instruction for a total of 128 bits.
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The basic instruction encoding looks as follows for a little-endian processor,
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The fields conforming an encoded basic instruction are stored in the
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where MSB and LSB mean the most significant bits and least significant bits,
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following order::
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respectively:
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============= ======= ======= ======= ============
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opcode:8 src_reg:4 dst_reg:4 offset:16 imm:32 // In little-endian BPF.
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32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB)
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opcode:8 dst_reg:4 src_reg:4 offset:16 imm:32 // In big-endian BPF.
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============= ======= ======= ======= ============
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imm offset src_reg dst_reg opcode
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============= ======= ======= ======= ============
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**imm**
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**imm**
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signed integer immediate value
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signed integer immediate value
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@ -64,16 +60,17 @@ imm offset src_reg dst_reg opcode
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**opcode**
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**opcode**
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operation to perform
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operation to perform
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and as follows for a big-endian processor:
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Note that the contents of multi-byte fields ('imm' and 'offset') are
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stored using big-endian byte ordering in big-endian BPF and
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little-endian byte ordering in little-endian BPF.
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============= ======= ======= ======= ============
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For example::
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32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB)
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============= ======= ======= ======= ============
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imm offset dst_reg src_reg opcode
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============= ======= ======= ======= ============
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Multi-byte fields ('imm' and 'offset') are similarly stored in
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opcode offset imm assembly
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the byte order of the processor.
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src_reg dst_reg
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07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little
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dst_reg src_reg
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07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big
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Note that most instructions do not use all of the fields.
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Note that most instructions do not use all of the fields.
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Unused fields shall be cleared to zero.
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Unused fields shall be cleared to zero.
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@ -84,18 +81,23 @@ The 64 bits following the basic instruction contain a pseudo instruction
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using the same format but with opcode, dst_reg, src_reg, and offset all set to zero,
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using the same format but with opcode, dst_reg, src_reg, and offset all set to zero,
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and imm containing the high 32 bits of the immediate value.
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and imm containing the high 32 bits of the immediate value.
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================= ==================
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This is depicted in the following figure::
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64 bits (MSB) 64 bits (LSB)
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================= ==================
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basic_instruction
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basic instruction pseudo instruction
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.-----------------------------.
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================= ==================
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code:8 regs:8 offset:16 imm:32 unused:32 imm:32
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'--------------'
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pseudo instruction
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Thus the 64-bit immediate value is constructed as follows:
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Thus the 64-bit immediate value is constructed as follows:
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imm64 = (next_imm << 32) | imm
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imm64 = (next_imm << 32) | imm
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where 'next_imm' refers to the imm value of the pseudo instruction
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where 'next_imm' refers to the imm value of the pseudo instruction
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following the basic instruction.
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following the basic instruction. The unused bytes in the pseudo
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instruction are reserved and shall be cleared to zero.
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Instruction classes
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Instruction classes
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-------------------
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-------------------
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