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drm/i915: rip out sanitize_pm again
We believe to have squashed all issues around the gen6+ rps interrupt generation and why the gpu sometimes got stuck. With that cleared up, there's no user left for the sanitize_pm infrastructure, so let's just rip it out. Note that 'intel_reg_write 0xa014 0x13070000' is the w/a if we find ourselves stuck again. Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -249,7 +249,6 @@ struct drm_i915_display_funcs {
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void (*update_wm)(struct drm_device *dev);
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void (*update_wm)(struct drm_device *dev);
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void (*update_sprite_wm)(struct drm_device *dev, int pipe,
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void (*update_sprite_wm)(struct drm_device *dev, int pipe,
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uint32_t sprite_width, int pixel_size);
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uint32_t sprite_width, int pixel_size);
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void (*sanitize_pm)(struct drm_device *dev);
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void (*update_linetime_wm)(struct drm_device *dev, int pipe,
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void (*update_linetime_wm)(struct drm_device *dev, int pipe,
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struct drm_display_mode *mode);
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struct drm_display_mode *mode);
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int (*crtc_mode_set)(struct drm_crtc *crtc,
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int (*crtc_mode_set)(struct drm_crtc *crtc,
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@ -5929,13 +5929,11 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
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void intel_mark_busy(struct drm_device *dev)
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void intel_mark_busy(struct drm_device *dev)
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{
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{
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intel_sanitize_pm(dev);
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i915_update_gfx_val(dev->dev_private);
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i915_update_gfx_val(dev->dev_private);
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}
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}
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void intel_mark_idle(struct drm_device *dev)
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void intel_mark_idle(struct drm_device *dev)
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{
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{
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intel_sanitize_pm(dev);
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}
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}
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void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
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void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
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@ -390,8 +390,6 @@ extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
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extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
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extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
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enum plane plane);
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enum plane plane);
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void intel_sanitize_pm(struct drm_device *dev);
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/* intel_panel.c */
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/* intel_panel.c */
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extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
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extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
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struct drm_display_mode *adjusted_mode);
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struct drm_display_mode *adjusted_mode);
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@ -2267,6 +2267,11 @@ static void ironlake_disable_drps(struct drm_device *dev)
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}
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}
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/* There's a funny hw issue where the hw returns all 0 when reading from
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* GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
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* ourselves, instead of doing a rmw cycle (which might result in us clearing
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* all limits and the gpu stuck at whatever frequency it is at atm).
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*/
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static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
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static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
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{
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{
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u32 limits;
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u32 limits;
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@ -3750,37 +3755,6 @@ void intel_init_clock_gating(struct drm_device *dev)
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dev_priv->display.init_pch_clock_gating(dev);
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dev_priv->display.init_pch_clock_gating(dev);
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}
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}
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static void gen6_sanitize_pm(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 limits, current_limits;
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gen6_gt_force_wake_get(dev_priv);
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current_limits = I915_READ(GEN6_RP_INTERRUPT_LIMITS);
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/* Make sure we continue to get interrupts
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* until we hit the minimum or maximum frequencies.
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*/
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limits = gen6_rps_limits(dev_priv, dev_priv->cur_delay);
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if (current_limits != limits) {
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/* Note that the known failure case is to read back 0. */
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DRM_DEBUG_DRIVER("Power management discrepancy: GEN6_RP_INTERRUPT_LIMITS "
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"expected %08x, was %08x\n", limits, current_limits);
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I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
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}
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gen6_gt_force_wake_put(dev_priv);
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}
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void intel_sanitize_pm(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->display.sanitize_pm)
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dev_priv->display.sanitize_pm(dev);
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}
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/* Starting with Haswell, we have different power wells for
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/* Starting with Haswell, we have different power wells for
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* different parts of the GPU. This attempts to enable them all.
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* different parts of the GPU. This attempts to enable them all.
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*/
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*/
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@ -3866,7 +3840,6 @@ void intel_init_pm(struct drm_device *dev)
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dev_priv->display.update_wm = NULL;
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dev_priv->display.update_wm = NULL;
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}
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}
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dev_priv->display.init_clock_gating = gen6_init_clock_gating;
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dev_priv->display.init_clock_gating = gen6_init_clock_gating;
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dev_priv->display.sanitize_pm = gen6_sanitize_pm;
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} else if (IS_IVYBRIDGE(dev)) {
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} else if (IS_IVYBRIDGE(dev)) {
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/* FIXME: detect B0+ stepping and use auto training */
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/* FIXME: detect B0+ stepping and use auto training */
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if (SNB_READ_WM0_LATENCY()) {
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if (SNB_READ_WM0_LATENCY()) {
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@ -3878,7 +3851,6 @@ void intel_init_pm(struct drm_device *dev)
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dev_priv->display.update_wm = NULL;
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dev_priv->display.update_wm = NULL;
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}
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}
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dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
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dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
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dev_priv->display.sanitize_pm = gen6_sanitize_pm;
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} else if (IS_HASWELL(dev)) {
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} else if (IS_HASWELL(dev)) {
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if (SNB_READ_WM0_LATENCY()) {
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if (SNB_READ_WM0_LATENCY()) {
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dev_priv->display.update_wm = sandybridge_update_wm;
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dev_priv->display.update_wm = sandybridge_update_wm;
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@ -3890,7 +3862,6 @@ void intel_init_pm(struct drm_device *dev)
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dev_priv->display.update_wm = NULL;
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dev_priv->display.update_wm = NULL;
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}
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}
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dev_priv->display.init_clock_gating = haswell_init_clock_gating;
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dev_priv->display.init_clock_gating = haswell_init_clock_gating;
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dev_priv->display.sanitize_pm = gen6_sanitize_pm;
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} else
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} else
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dev_priv->display.update_wm = NULL;
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dev_priv->display.update_wm = NULL;
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} else if (IS_VALLEYVIEW(dev)) {
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} else if (IS_VALLEYVIEW(dev)) {
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