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https://github.com/torvalds/linux
synced 2024-10-09 21:05:10 +00:00
clk: at91: sckc: add support to specify registers bit offsets
Different IPs uses different bit offsets in registers for the same functionality, thus adapt the driver to support this. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Claudiu Beznea
Stephen Boyd
parent
5cf6d876a7
commit
abaceffc88
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@ -23,14 +23,18 @@
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SLOW_CLOCK_FREQ)
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#define AT91_SCKC_CR 0x00
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#define AT91_SCKC_RCEN (1 << 0)
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#define AT91_SCKC_OSC32EN (1 << 1)
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#define AT91_SCKC_OSC32BYP (1 << 2)
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#define AT91_SCKC_OSCSEL (1 << 3)
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struct clk_slow_bits {
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u32 cr_rcen;
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u32 cr_osc32en;
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u32 cr_osc32byp;
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u32 cr_oscsel;
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};
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struct clk_slow_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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const struct clk_slow_bits *bits;
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unsigned long startup_usec;
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};
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@ -39,6 +43,7 @@ struct clk_slow_osc {
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struct clk_sama5d4_slow_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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const struct clk_slow_bits *bits;
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unsigned long startup_usec;
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bool prepared;
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};
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@ -48,6 +53,7 @@ struct clk_sama5d4_slow_osc {
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struct clk_slow_rc_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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const struct clk_slow_bits *bits;
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unsigned long frequency;
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unsigned long accuracy;
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unsigned long startup_usec;
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@ -58,6 +64,7 @@ struct clk_slow_rc_osc {
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struct clk_sam9x5_slow {
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struct clk_hw hw;
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void __iomem *sckcr;
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const struct clk_slow_bits *bits;
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u8 parent;
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};
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@ -69,10 +76,10 @@ static int clk_slow_osc_prepare(struct clk_hw *hw)
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & (AT91_SCKC_OSC32BYP | AT91_SCKC_OSC32EN))
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if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en))
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return 0;
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writel(tmp | AT91_SCKC_OSC32EN, sckcr);
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writel(tmp | osc->bits->cr_osc32en, sckcr);
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usleep_range(osc->startup_usec, osc->startup_usec + 1);
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@ -85,10 +92,10 @@ static void clk_slow_osc_unprepare(struct clk_hw *hw)
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & AT91_SCKC_OSC32BYP)
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if (tmp & osc->bits->cr_osc32byp)
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return;
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writel(tmp & ~AT91_SCKC_OSC32EN, sckcr);
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writel(tmp & ~osc->bits->cr_osc32en, sckcr);
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}
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static int clk_slow_osc_is_prepared(struct clk_hw *hw)
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@ -97,10 +104,10 @@ static int clk_slow_osc_is_prepared(struct clk_hw *hw)
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & AT91_SCKC_OSC32BYP)
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if (tmp & osc->bits->cr_osc32byp)
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return 1;
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return !!(tmp & AT91_SCKC_OSC32EN);
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return !!(tmp & osc->bits->cr_osc32en);
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}
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static const struct clk_ops slow_osc_ops = {
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@ -114,7 +121,8 @@ at91_clk_register_slow_osc(void __iomem *sckcr,
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const char *name,
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const char *parent_name,
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unsigned long startup,
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bool bypass)
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bool bypass,
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const struct clk_slow_bits *bits)
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{
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struct clk_slow_osc *osc;
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struct clk_hw *hw;
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@ -137,10 +145,11 @@ at91_clk_register_slow_osc(void __iomem *sckcr,
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osc->hw.init = &init;
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osc->sckcr = sckcr;
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osc->startup_usec = startup;
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osc->bits = bits;
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if (bypass)
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writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP,
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sckcr);
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writel((readl(sckcr) & ~osc->bits->cr_osc32en) |
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osc->bits->cr_osc32byp, sckcr);
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hw = &osc->hw;
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ret = clk_hw_register(NULL, &osc->hw);
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@ -173,7 +182,7 @@ static int clk_slow_rc_osc_prepare(struct clk_hw *hw)
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr);
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writel(readl(sckcr) | osc->bits->cr_rcen, sckcr);
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usleep_range(osc->startup_usec, osc->startup_usec + 1);
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@ -185,14 +194,14 @@ static void clk_slow_rc_osc_unprepare(struct clk_hw *hw)
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr);
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writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr);
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}
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static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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return !!(readl(osc->sckcr) & AT91_SCKC_RCEN);
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return !!(readl(osc->sckcr) & osc->bits->cr_rcen);
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}
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static const struct clk_ops slow_rc_osc_ops = {
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@ -208,7 +217,8 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr,
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const char *name,
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unsigned long frequency,
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unsigned long accuracy,
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unsigned long startup)
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unsigned long startup,
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const struct clk_slow_bits *bits)
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{
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struct clk_slow_rc_osc *osc;
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struct clk_hw *hw;
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@ -230,6 +240,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr,
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osc->hw.init = &init;
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osc->sckcr = sckcr;
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osc->bits = bits;
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osc->frequency = frequency;
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osc->accuracy = accuracy;
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osc->startup_usec = startup;
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@ -255,14 +266,14 @@ static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index)
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tmp = readl(sckcr);
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if ((!index && !(tmp & AT91_SCKC_OSCSEL)) ||
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(index && (tmp & AT91_SCKC_OSCSEL)))
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if ((!index && !(tmp & slowck->bits->cr_oscsel)) ||
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(index && (tmp & slowck->bits->cr_oscsel)))
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return 0;
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if (index)
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tmp |= AT91_SCKC_OSCSEL;
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tmp |= slowck->bits->cr_oscsel;
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else
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tmp &= ~AT91_SCKC_OSCSEL;
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tmp &= ~slowck->bits->cr_oscsel;
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writel(tmp, sckcr);
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@ -275,7 +286,7 @@ static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
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{
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struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
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return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL);
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return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel);
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}
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static const struct clk_ops sam9x5_slow_ops = {
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@ -287,7 +298,8 @@ static struct clk_hw * __init
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at91_clk_register_sam9x5_slow(void __iomem *sckcr,
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const char *name,
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const char **parent_names,
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int num_parents)
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int num_parents,
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const struct clk_slow_bits *bits)
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{
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struct clk_sam9x5_slow *slowck;
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struct clk_hw *hw;
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@ -309,7 +321,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
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slowck->hw.init = &init;
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slowck->sckcr = sckcr;
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slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL);
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slowck->bits = bits;
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slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel);
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hw = &slowck->hw;
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ret = clk_hw_register(NULL, &slowck->hw);
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@ -322,7 +335,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
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}
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static void __init at91sam9x5_sckc_register(struct device_node *np,
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unsigned int rc_osc_startup_us)
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unsigned int rc_osc_startup_us,
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const struct clk_slow_bits *bits)
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{
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const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
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void __iomem *regbase = of_iomap(np, 0);
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@ -335,7 +349,8 @@ static void __init at91sam9x5_sckc_register(struct device_node *np,
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return;
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hw = at91_clk_register_slow_rc_osc(regbase, parent_names[0], 32768,
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50000000, rc_osc_startup_us);
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50000000, rc_osc_startup_us,
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bits);
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if (IS_ERR(hw))
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return;
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@ -358,11 +373,12 @@ static void __init at91sam9x5_sckc_register(struct device_node *np,
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return;
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hw = at91_clk_register_slow_osc(regbase, parent_names[1], xtal_name,
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1200000, bypass);
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1200000, bypass, bits);
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if (IS_ERR(hw))
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return;
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hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2);
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hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2,
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bits);
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if (IS_ERR(hw))
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return;
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@ -373,16 +389,23 @@ static void __init at91sam9x5_sckc_register(struct device_node *np,
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of_clk_add_hw_provider(child, of_clk_hw_simple_get, hw);
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}
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static const struct clk_slow_bits at91sam9x5_bits = {
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.cr_rcen = BIT(0),
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.cr_osc32en = BIT(1),
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.cr_osc32byp = BIT(2),
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.cr_oscsel = BIT(3),
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};
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static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
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{
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at91sam9x5_sckc_register(np, 75);
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at91sam9x5_sckc_register(np, 75, &at91sam9x5_bits);
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}
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CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
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of_at91sam9x5_sckc_setup);
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static void __init of_sama5d3_sckc_setup(struct device_node *np)
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{
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at91sam9x5_sckc_register(np, 500);
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at91sam9x5_sckc_register(np, 500, &at91sam9x5_bits);
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}
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CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc",
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of_sama5d3_sckc_setup);
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@ -398,7 +421,7 @@ static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw)
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* Assume that if it has already been selected (for example by the
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* bootloader), enough time has aready passed.
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*/
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if ((readl(osc->sckcr) & AT91_SCKC_OSCSEL)) {
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if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) {
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osc->prepared = true;
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return 0;
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}
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@ -421,6 +444,10 @@ static const struct clk_ops sama5d4_slow_osc_ops = {
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.is_prepared = clk_sama5d4_slow_osc_is_prepared,
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};
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static const struct clk_slow_bits at91sama5d4_bits = {
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.cr_oscsel = BIT(3),
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};
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static void __init of_sama5d4_sckc_setup(struct device_node *np)
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{
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void __iomem *regbase = of_iomap(np, 0);
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@ -455,6 +482,7 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np)
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osc->hw.init = &init;
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osc->sckcr = regbase;
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osc->startup_usec = 1200000;
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osc->bits = &at91sama5d4_bits;
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hw = &osc->hw;
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ret = clk_hw_register(NULL, &osc->hw);
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@ -463,7 +491,8 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np)
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return;
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}
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hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2);
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hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2,
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&at91sama5d4_bits);
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if (IS_ERR(hw))
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return;
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