mirror of
https://github.com/torvalds/linux
synced 2024-07-23 03:29:48 +00:00
MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option
Use a new config option to enable MIPS 34K ITLB workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
parent
256ec489f1
commit
a7fbed988f
|
@ -2683,6 +2683,10 @@ config WAR_ICACHE_REFILLS
|
||||||
config WAR_R10000_LLSC
|
config WAR_R10000_LLSC
|
||||||
bool
|
bool
|
||||||
|
|
||||||
|
# 34K core erratum: "Problems Executing the TLBR Instruction"
|
||||||
|
config WAR_MIPS34K_MISSED_ITLB
|
||||||
|
bool
|
||||||
|
|
||||||
#
|
#
|
||||||
# - Highmem only makes sense for the 32-bit kernel.
|
# - Highmem only makes sense for the 32-bit kernel.
|
||||||
# - The current highmem code will only work properly on physically indexed
|
# - The current highmem code will only work properly on physically indexed
|
||||||
|
|
|
@ -11,7 +11,6 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
|
#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
|
||||||
OCTEON_IS_MODEL(OCTEON_CN6XXX)
|
OCTEON_IS_MODEL(OCTEON_CN6XXX)
|
||||||
|
|
|
@ -10,6 +10,5 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MACH_GENERIC_WAR_H */
|
#endif /* __ASM_MACH_GENERIC_WAR_H */
|
||||||
|
|
|
@ -10,6 +10,5 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
|
#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
|
||||||
|
|
|
@ -10,6 +10,5 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
|
#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
|
||||||
|
|
|
@ -10,6 +10,5 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
|
#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
|
||||||
|
|
|
@ -7,6 +7,5 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */
|
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */
|
||||||
|
|
|
@ -10,6 +10,5 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
|
#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
|
||||||
|
|
|
@ -10,6 +10,5 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
|
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
|
||||||
|
|
|
@ -10,6 +10,5 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
|
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
|
||||||
|
|
|
@ -10,6 +10,5 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MIPS_MACH_RM_WAR_H */
|
#endif /* __ASM_MIPS_MACH_RM_WAR_H */
|
||||||
|
|
|
@ -24,6 +24,4 @@ extern int sb1250_m3_workaround_needed(void);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
|
#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
|
||||||
|
|
|
@ -10,6 +10,5 @@
|
||||||
|
|
||||||
#define BCM1250_M3_WAR 0
|
#define BCM1250_M3_WAR 0
|
||||||
#define SIBYTE_1956_WAR 0
|
#define SIBYTE_1956_WAR 0
|
||||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
||||||
|
|
||||||
#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
|
#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
|
||||||
|
|
|
@ -2716,7 +2716,7 @@ static inline void tlb_probe(void)
|
||||||
|
|
||||||
static inline void tlb_read(void)
|
static inline void tlb_read(void)
|
||||||
{
|
{
|
||||||
#if MIPS34K_MISSED_ITLB_WAR
|
#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
|
||||||
int res = 0;
|
int res = 0;
|
||||||
|
|
||||||
__asm__ __volatile__(
|
__asm__ __volatile__(
|
||||||
|
@ -2738,7 +2738,7 @@ static inline void tlb_read(void)
|
||||||
"tlbr\n\t"
|
"tlbr\n\t"
|
||||||
".set reorder");
|
".set reorder");
|
||||||
|
|
||||||
#if MIPS34K_MISSED_ITLB_WAR
|
#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
|
||||||
if ((res & _ULCAST_(1)))
|
if ((res & _ULCAST_(1)))
|
||||||
__asm__ __volatile__(
|
__asm__ __volatile__(
|
||||||
" .set push \n"
|
" .set push \n"
|
||||||
|
|
|
@ -93,11 +93,4 @@
|
||||||
#error Check setting of SIBYTE_1956_WAR for your platform
|
#error Check setting of SIBYTE_1956_WAR for your platform
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*
|
|
||||||
* 34K core erratum: "Problems Executing the TLBR Instruction"
|
|
||||||
*/
|
|
||||||
#ifndef MIPS34K_MISSED_ITLB_WAR
|
|
||||||
#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _ASM_WAR_H */
|
#endif /* _ASM_WAR_H */
|
||||||
|
|
Loading…
Reference in a new issue