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drm/amd/display: Multi-display underflow observed
[Why] FP2 programming not happening when topology changes occur with multiple displays. [How] Ensure FP2 is programmed whenever global sync changes occur but wait for VACTIVE first to avoid underflow. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2625,26 +2625,6 @@ static void commit_planes_for_stream(struct dc *dc,
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}
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}
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if (update_type != UPDATE_TYPE_FAST) {
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// If changing VTG FP2: wait until back in vactive to program FP2
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// Need to ensure that pipe unlock happens soon after to minimize race condition
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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if (pipe_ctx->top_pipe || pipe_ctx->stream != stream)
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continue;
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if (!pipe_ctx->update_flags.bits.global_sync)
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continue;
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pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
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pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
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pipe_ctx->stream_res.tg->funcs->set_vtg_params(
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pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
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}
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}
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if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
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dc->hwss.interdependent_update_lock(dc, context, false);
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else
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@ -1586,7 +1586,10 @@ static void dcn20_program_pipe(
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&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
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hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
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if (pipe_ctx->update_flags.bits.global_sync) {
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/* Only update TG on top pipe */
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if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
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&& !pipe_ctx->prev_odm_pipe) {
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pipe_ctx->stream_res.tg->funcs->program_global_sync(
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pipe_ctx->stream_res.tg,
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pipe_ctx->pipe_dlg_param.vready_offset,
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@ -1594,8 +1597,11 @@ static void dcn20_program_pipe(
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pipe_ctx->pipe_dlg_param.vupdate_offset,
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pipe_ctx->pipe_dlg_param.vupdate_width);
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pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
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pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
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pipe_ctx->stream_res.tg->funcs->set_vtg_params(
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pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
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pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
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if (hws->funcs.setup_vupdate_interrupt)
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hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
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