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parisc: disable preemption during local tlb flush
flush_cache_mm() and flush_cache_range() fetch %sr3 via mfsp(). If it matches mm->context, they flush caches and the TLB. However, the TLB is cpu-local, so if the code gets preempted shortly after the mfsp(), and later resumed on another CPU, the wrong TLB is flushed. Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Helge Deller <deller@gmx.de>
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@ -558,6 +558,7 @@ void flush_cache_mm(struct mm_struct *mm)
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return;
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}
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preempt_disable();
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if (mm->context == mfsp(3)) {
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for (vma = mm->mmap; vma; vma = vma->vm_next) {
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flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
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@ -565,6 +566,7 @@ void flush_cache_mm(struct mm_struct *mm)
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flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
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flush_tlb_range(vma, vma->vm_start, vma->vm_end);
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}
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preempt_enable();
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return;
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}
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@ -589,6 +591,7 @@ void flush_cache_mm(struct mm_struct *mm)
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}
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}
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}
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preempt_enable();
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}
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void flush_cache_range(struct vm_area_struct *vma,
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@ -605,11 +608,13 @@ void flush_cache_range(struct vm_area_struct *vma,
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return;
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}
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preempt_disable();
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if (vma->vm_mm->context == mfsp(3)) {
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flush_user_dcache_range_asm(start, end);
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if (vma->vm_flags & VM_EXEC)
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flush_user_icache_range_asm(start, end);
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flush_tlb_range(vma, start, end);
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preempt_enable();
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return;
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}
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@ -629,6 +634,7 @@ void flush_cache_range(struct vm_area_struct *vma,
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}
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}
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}
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preempt_enable();
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}
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void
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