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parisc: disable preemption during local tlb flush

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flush_cache_mm() and flush_cache_range() fetch %sr3 via mfsp().
If it matches mm->context, they flush caches and the TLB. However,
the TLB is cpu-local, so if the code gets preempted shortly after
the mfsp(), and later resumed on another CPU, the wrong TLB is flushed.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
Sven Schnelle 2021-10-09 20:24:35 +02:00 committed by Helge Deller
parent ec5c115050
commit a5e8ca3783
1 changed files with 6 additions and 0 deletions
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6
arch/parisc/kernel/cache.c
View file

@ -558,6 +558,7 @@ void flush_cache_mm(struct mm_struct *mm)
return;
}
preempt_disable();
if (mm->context == mfsp(3)) {
for (vma = mm->mmap; vma; vma = vma->vm_next) {
flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
@ -565,6 +566,7 @@ void flush_cache_mm(struct mm_struct *mm)
flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
flush_tlb_range(vma, vma->vm_start, vma->vm_end);
}
preempt_enable();
return;
}
@ -589,6 +591,7 @@ void flush_cache_mm(struct mm_struct *mm)
}
}
}
preempt_enable();
}
void flush_cache_range(struct vm_area_struct *vma,
@ -605,11 +608,13 @@ void flush_cache_range(struct vm_area_struct *vma,
return;
}
preempt_disable();
if (vma->vm_mm->context == mfsp(3)) {
flush_user_dcache_range_asm(start, end);
if (vma->vm_flags & VM_EXEC)
flush_user_icache_range_asm(start, end);
flush_tlb_range(vma, start, end);
preempt_enable();
return;
}
@ -629,6 +634,7 @@ void flush_cache_range(struct vm_area_struct *vma,
}
}
}
preempt_enable();
}
void