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https://github.com/torvalds/linux
synced 2024-09-06 18:01:05 +00:00
ALSA: emu10k1: fix access to Audigy GPIO port
As the register definition clearly states, this is a 16-bit register, yet we did all accesses as 32-bit. The writes in particular would have the potential to clear the TIMER register (depending on how the bus/card actually handles the too long writes). This commit also introduces a separate define A_GPIO which aliases A_IOCFG, which better reflects the distinct usage on E-MU cards. This is done in the same commit to keep the churn down, as we're touching all involved lines anyway. Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de> Link: https://lore.kernel.org/r/20230421141006.1005539-2-oswald.buddenhagen@gmx.de Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
parent
10f212bd7a
commit
a1c87c0b27
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@ -251,11 +251,16 @@
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#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
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#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
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#define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
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#define A_GPIO 0x18 /* GPIO on Audigy card (16bits) */
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#define A_GPINPUT_MASK 0xff00
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#define A_GPOUTPUT_MASK 0x00ff
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// The GPIO port is used for I/O config on Sound Blasters;
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// card-specific info can be found in the emu_chip_details table.
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// On E-MU cards the port is used as the interface to the FPGA.
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// Audigy output/GPIO stuff taken from the kX drivers
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#define A_IOCFG A_GPIO
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#define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
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#define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
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#define A_IOCFG_ENABLE_DIGITAL 0x0004
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@ -223,8 +223,8 @@ static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
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*/
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outl(0x7a0000, emu->port + 0x20);
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outl(0xFF000000, emu->port + 0x24);
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tmp = inl(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */
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outl(tmp, emu->port + A_IOCFG);
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tmp = inw(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */
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outw(tmp, emu->port + A_IOCFG);
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}
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if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */
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int size, n;
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@ -244,15 +244,15 @@ static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
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* GPIO6: Unknown
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* GPIO7: Unknown
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*/
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outl(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */
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outw(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */
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}
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if (emu->card_capabilities->i2c_adc) { /* Audigy 2 ZS Notebook with ADC Wolfson WM8775 */
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int size, n;
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snd_emu10k1_ptr20_write(emu, P17V_I2S_SRC_SEL, 0, 0x2020205f);
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tmp = inl(emu->port + A_IOCFG);
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outl(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */
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tmp = inl(emu->port + A_IOCFG);
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tmp = inw(emu->port + A_IOCFG);
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outw(tmp | 0x4, emu->port + A_IOCFG); /* Set bit 2 for mic input */
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tmp = inw(emu->port + A_IOCFG);
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size = ARRAY_SIZE(i2c_adc_init);
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for (n = 0; n < size; n++)
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snd_emu10k1_i2c_write(emu, i2c_adc_init[n][0], i2c_adc_init[n][1]);
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@ -308,12 +308,12 @@ static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
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} else if (emu->card_capabilities->i2c_adc) {
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; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
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} else if (emu->audigy) {
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unsigned int reg = inl(emu->port + A_IOCFG);
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outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
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u16 reg = inw(emu->port + A_IOCFG);
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outw(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
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udelay(500);
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outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
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outw(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
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udelay(100);
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outl(reg, emu->port + A_IOCFG);
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outw(reg, emu->port + A_IOCFG);
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} else {
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unsigned int reg = inl(emu->port + HCFG);
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outl(reg | HCFG_GPOUT2, emu->port + HCFG);
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@ -329,8 +329,8 @@ static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
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} else if (emu->card_capabilities->i2c_adc) {
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; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
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} else if (emu->audigy) { /* enable analog output */
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unsigned int reg = inl(emu->port + A_IOCFG);
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outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
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u16 reg = inw(emu->port + A_IOCFG);
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outw(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
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}
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if (emu->address_mode == 0) {
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@ -354,19 +354,19 @@ static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu)
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} else if (emu->card_capabilities->i2c_adc) {
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; /* Disable A_IOCFG for Audigy 2 ZS Notebook */
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} else if (emu->audigy) {
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outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
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outw(inw(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
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if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
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/* Unmute Analog now. Set GPO6 to 1 for Apollo.
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* This has to be done after init ALice3 I2SOut beyond 48KHz.
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* So, sequence is important. */
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outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
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outw(inw(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
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} else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */
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/* Unmute Analog now. */
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outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
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outw(inw(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
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} else {
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/* Disable routing from AC97 line out to Front speakers */
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outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
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outw(inw(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
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}
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}
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@ -651,9 +651,9 @@ static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu,
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const struct firmware *fw_entry)
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{
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int n, i;
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int reg;
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int value;
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__always_unused unsigned int write_post;
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u16 reg;
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u8 value;
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__always_unused u16 write_post;
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unsigned long flags;
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if (!fw_entry)
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@ -666,11 +666,11 @@ static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu,
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* FPGA CONFIG OFF -> FPGA PGMN
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*/
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spin_lock_irqsave(&emu->emu_lock, flags);
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outl(0x00, emu->port + A_IOCFG); /* Set PGMN low for 1uS. */
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write_post = inl(emu->port + A_IOCFG);
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outw(0x00, emu->port + A_GPIO); /* Set PGMN low for 1uS. */
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write_post = inw(emu->port + A_GPIO);
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udelay(100);
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outl(0x80, emu->port + A_IOCFG); /* Leave bit 7 set during netlist setup. */
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write_post = inl(emu->port + A_IOCFG);
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outw(0x80, emu->port + A_GPIO); /* Leave bit 7 set during netlist setup. */
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write_post = inw(emu->port + A_GPIO);
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udelay(100); /* Allow FPGA memory to clean */
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for (n = 0; n < fw_entry->size; n++) {
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value = fw_entry->data[n];
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@ -679,15 +679,15 @@ static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu,
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if (value & 0x1)
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reg = reg | 0x20;
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value = value >> 1;
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outl(reg, emu->port + A_IOCFG);
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write_post = inl(emu->port + A_IOCFG);
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outl(reg | 0x40, emu->port + A_IOCFG);
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write_post = inl(emu->port + A_IOCFG);
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outw(reg, emu->port + A_GPIO);
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write_post = inw(emu->port + A_GPIO);
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outw(reg | 0x40, emu->port + A_GPIO);
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write_post = inw(emu->port + A_GPIO);
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}
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}
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/* After programming, set GPIO bit 4 high again. */
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outl(0x10, emu->port + A_IOCFG);
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write_post = inl(emu->port + A_IOCFG);
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outw(0x10, emu->port + A_GPIO);
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write_post = inw(emu->port + A_GPIO);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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return 0;
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@ -2053,7 +2053,7 @@ void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu)
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*val = snd_emu10k1_ptr_read(emu, *reg, i);
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}
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if (emu->audigy)
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emu->saved_a_iocfg = inl(emu->port + A_IOCFG);
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emu->saved_a_iocfg = inw(emu->port + A_IOCFG);
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emu->saved_hcfg = inl(emu->port + HCFG);
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}
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@ -2080,7 +2080,7 @@ void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu)
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/* resore for spdif */
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if (emu->audigy)
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outl(emu->saved_a_iocfg, emu->port + A_IOCFG);
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outw(emu->saved_a_iocfg, emu->port + A_IOCFG);
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outl(emu->saved_hcfg, emu->port + HCFG);
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val = emu->saved_ptr;
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@ -924,7 +924,7 @@ static int snd_audigy_i2c_capture_source_put(struct snd_kcontrol *kcontrol,
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struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
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unsigned int source_id;
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unsigned int ngain, ogain;
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u32 gpio;
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u16 gpio;
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int change = 0;
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unsigned long flags;
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u32 source;
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@ -941,11 +941,11 @@ static int snd_audigy_i2c_capture_source_put(struct snd_kcontrol *kcontrol,
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if (change) {
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snd_emu10k1_i2c_write(emu, ADC_MUX, 0); /* Mute input */
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spin_lock_irqsave(&emu->emu_lock, flags);
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gpio = inl(emu->port + A_IOCFG);
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gpio = inw(emu->port + A_IOCFG);
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if (source_id==0)
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outl(gpio | 0x4, emu->port + A_IOCFG);
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outw(gpio | 0x4, emu->port + A_IOCFG);
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else
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outl(gpio & ~0x4, emu->port + A_IOCFG);
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outw(gpio & ~0x4, emu->port + A_IOCFG);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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ngain = emu->i2c_capture_volume[source_id][0]; /* Left */
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@ -1632,7 +1632,7 @@ static int snd_emu10k1_shared_spdif_get(struct snd_kcontrol *kcontrol,
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struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
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if (emu->audigy)
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ucontrol->value.integer.value[0] = inl(emu->port + A_IOCFG) & A_IOCFG_GPOUT0 ? 1 : 0;
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ucontrol->value.integer.value[0] = inw(emu->port + A_IOCFG) & A_IOCFG_GPOUT0 ? 1 : 0;
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else
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ucontrol->value.integer.value[0] = inl(emu->port + HCFG) & HCFG_GPOUT0 ? 1 : 0;
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if (emu->card_capabilities->invert_shared_spdif)
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@ -1657,13 +1657,13 @@ static int snd_emu10k1_shared_spdif_put(struct snd_kcontrol *kcontrol,
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if ( emu->card_capabilities->i2c_adc) {
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/* Do nothing for Audigy 2 ZS Notebook */
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} else if (emu->audigy) {
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reg = inl(emu->port + A_IOCFG);
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reg = inw(emu->port + A_IOCFG);
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val = sw ? A_IOCFG_GPOUT0 : 0;
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change = (reg & A_IOCFG_GPOUT0) != val;
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if (change) {
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reg &= ~A_IOCFG_GPOUT0;
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reg |= val;
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outl(reg | val, emu->port + A_IOCFG);
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outw(reg | val, emu->port + A_IOCFG);
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}
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}
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reg = inl(emu->port + HCFG);
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@ -243,13 +243,13 @@ void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value)
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if (snd_BUG_ON(value > 0x3f)) /* 0 to 0x3f are values */
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return;
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spin_lock_irqsave(&emu->emu_lock, flags);
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outl(reg, emu->port + A_IOCFG);
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outw(reg, emu->port + A_GPIO);
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udelay(10);
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outl(reg | 0x80, emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */
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outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
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udelay(10);
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outl(value, emu->port + A_IOCFG);
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outw(value, emu->port + A_GPIO);
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udelay(10);
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outl(value | 0x80 , emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */
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outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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}
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@ -260,11 +260,11 @@ void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value)
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return;
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reg += 0x40; /* 0x40 upwards are registers. */
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spin_lock_irqsave(&emu->emu_lock, flags);
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outl(reg, emu->port + A_IOCFG);
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outw(reg, emu->port + A_GPIO);
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udelay(10);
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outl(reg | 0x80, emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */
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outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
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udelay(10);
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*value = ((inl(emu->port + A_IOCFG) >> 8) & 0x7f);
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*value = ((inw(emu->port + A_GPIO) >> 8) & 0x7f);
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spin_unlock_irqrestore(&emu->emu_lock, flags);
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}
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