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https://github.com/torvalds/linux
synced 2024-10-14 23:39:09 +00:00
drm/amd/display: fix i386 frame size warning
Addresses the following warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:3596:6: error: stack frame size (2092) exceeds limit (2048) in 'dml30_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than]
void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
^
UseMinimumDCFCLK() is eating away at
dml30_ModeSupportAndSystemConfigurationFull()'s stack space, so use a
pointer to struct vba_vars_st instead of passing lots of large arrays
as parameters by value.
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hamza Mahfooz
Alex Deucher
parent
947f63f17e
commit
a0f7e7f759
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@ -396,64 +396,10 @@ static void CalculateUrgentBurstFactor(
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static void UseMinimumDCFCLK(
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struct display_mode_lib *mode_lib,
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int MaxInterDCNTileRepeaters,
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struct vba_vars_st *v,
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int MaxPrefetchMode,
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double FinalDRAMClockChangeLatency,
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double SREnterPlusExitTime,
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int ReturnBusWidth,
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int RoundTripPingLatencyCycles,
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int ReorderingBytes,
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int PixelChunkSizeInKByte,
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int MetaChunkSize,
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bool GPUVMEnable,
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int GPUVMMaxPageTableLevels,
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bool HostVMEnable,
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int NumberOfActivePlanes,
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double HostVMMinPageSize,
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int HostVMMaxNonCachedPageTableLevels,
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bool DynamicMetadataVMEnabled,
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enum immediate_flip_requirement ImmediateFlipRequirement,
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bool ProgressiveToInterlaceUnitInOPP,
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double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
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double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
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double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
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double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly,
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int VTotal[],
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int VActive[],
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int DynamicMetadataTransmittedBytes[],
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int DynamicMetadataLinesBeforeActiveRequired[],
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bool Interlace[],
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double RequiredDPPCLK[][2][DC__NUM_DPP__MAX],
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double RequiredDISPCLK[][2],
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double UrgLatency[],
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unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
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double ProjectedDCFCLKDeepSleep[][2],
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double MaximumVStartup[][2][DC__NUM_DPP__MAX],
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double TotalVActivePixelBandwidth[][2],
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double TotalVActiveCursorBandwidth[][2],
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double TotalMetaRowBandwidth[][2],
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double TotalDPTERowBandwidth[][2],
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unsigned int TotalNumberOfActiveDPP[][2],
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unsigned int TotalNumberOfDCCActiveDPP[][2],
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int dpte_group_bytes[],
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double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
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double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
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unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
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unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
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int BytePerPixelY[],
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int BytePerPixelC[],
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int HTotal[],
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double PixelClock[],
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double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
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double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
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double MetaRowBytes[][2][DC__NUM_DPP__MAX],
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bool DynamicMetadataEnable[],
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double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX],
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double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX],
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double ReadBandwidthLuma[],
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double ReadBandwidthChroma[],
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double DCFCLKPerState[],
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double DCFCLKState[][2]);
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int ReorderingBytes);
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static void CalculatePixelDeliveryTimes(
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unsigned int NumberOfActivePlanes,
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double VRatio[],
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@ -4692,66 +4638,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
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}
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if (v->UseMinimumRequiredDCFCLK == true) {
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UseMinimumDCFCLK(
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mode_lib,
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v->MaxInterDCNTileRepeaters,
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MaxPrefetchMode,
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v->FinalDRAMClockChangeLatency,
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v->SREnterPlusExitTime,
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v->ReturnBusWidth,
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v->RoundTripPingLatencyCycles,
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ReorderingBytes,
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v->PixelChunkSizeInKByte,
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v->MetaChunkSize,
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v->GPUVMEnable,
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v->GPUVMMaxPageTableLevels,
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v->HostVMEnable,
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v->NumberOfActivePlanes,
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v->HostVMMinPageSize,
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v->HostVMMaxNonCachedPageTableLevels,
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v->DynamicMetadataVMEnabled,
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v->ImmediateFlipRequirement[0],
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v->ProgressiveToInterlaceUnitInOPP,
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v->MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
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v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
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v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
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v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly,
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v->VTotal,
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v->VActive,
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v->DynamicMetadataTransmittedBytes,
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v->DynamicMetadataLinesBeforeActiveRequired,
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v->Interlace,
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v->RequiredDPPCLK,
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v->RequiredDISPCLK,
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v->UrgLatency,
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v->NoOfDPP,
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v->ProjectedDCFCLKDeepSleep,
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v->MaximumVStartup,
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v->TotalVActivePixelBandwidth,
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v->TotalVActiveCursorBandwidth,
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v->TotalMetaRowBandwidth,
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v->TotalDPTERowBandwidth,
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v->TotalNumberOfActiveDPP,
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v->TotalNumberOfDCCActiveDPP,
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v->dpte_group_bytes,
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v->PrefetchLinesY,
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v->PrefetchLinesC,
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v->swath_width_luma_ub_all_states,
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v->swath_width_chroma_ub_all_states,
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v->BytePerPixelY,
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v->BytePerPixelC,
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v->HTotal,
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v->PixelClock,
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v->PDEAndMetaPTEBytesPerFrame,
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v->DPTEBytesPerRow,
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v->MetaRowBytes,
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v->DynamicMetadataEnable,
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v->VActivePixelBandwidth,
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v->VActiveCursorBandwidth,
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v->ReadBandwidthLuma,
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v->ReadBandwidthChroma,
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v->DCFCLKPerState,
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v->DCFCLKState);
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UseMinimumDCFCLK(mode_lib, v, MaxPrefetchMode, ReorderingBytes);
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if (v->ClampMinDCFCLK) {
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/* Clamp calculated values to actual minimum */
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@ -6610,77 +6497,21 @@ static double CalculateUrgentLatency(
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return ret;
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}
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static void UseMinimumDCFCLK(
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struct display_mode_lib *mode_lib,
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int MaxInterDCNTileRepeaters,
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struct vba_vars_st *v,
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int MaxPrefetchMode,
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double FinalDRAMClockChangeLatency,
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double SREnterPlusExitTime,
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int ReturnBusWidth,
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int RoundTripPingLatencyCycles,
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int ReorderingBytes,
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int PixelChunkSizeInKByte,
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int MetaChunkSize,
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bool GPUVMEnable,
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int GPUVMMaxPageTableLevels,
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bool HostVMEnable,
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int NumberOfActivePlanes,
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double HostVMMinPageSize,
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int HostVMMaxNonCachedPageTableLevels,
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bool DynamicMetadataVMEnabled,
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enum immediate_flip_requirement ImmediateFlipRequirement,
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bool ProgressiveToInterlaceUnitInOPP,
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double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
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double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
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double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
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double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly,
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int VTotal[],
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int VActive[],
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int DynamicMetadataTransmittedBytes[],
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int DynamicMetadataLinesBeforeActiveRequired[],
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bool Interlace[],
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double RequiredDPPCLK[][2][DC__NUM_DPP__MAX],
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double RequiredDISPCLK[][2],
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double UrgLatency[],
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unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
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double ProjectedDCFCLKDeepSleep[][2],
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double MaximumVStartup[][2][DC__NUM_DPP__MAX],
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double TotalVActivePixelBandwidth[][2],
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double TotalVActiveCursorBandwidth[][2],
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double TotalMetaRowBandwidth[][2],
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double TotalDPTERowBandwidth[][2],
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unsigned int TotalNumberOfActiveDPP[][2],
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unsigned int TotalNumberOfDCCActiveDPP[][2],
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int dpte_group_bytes[],
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double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
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double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
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unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
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unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
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int BytePerPixelY[],
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int BytePerPixelC[],
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int HTotal[],
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double PixelClock[],
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double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
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double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
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double MetaRowBytes[][2][DC__NUM_DPP__MAX],
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bool DynamicMetadataEnable[],
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double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX],
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double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX],
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double ReadBandwidthLuma[],
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double ReadBandwidthChroma[],
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double DCFCLKPerState[],
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double DCFCLKState[][2])
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int ReorderingBytes)
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{
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double NormalEfficiency = 0;
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double PTEEfficiency = 0;
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double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } };
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unsigned int i, j, k;
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NormalEfficiency = (HostVMEnable == true ? PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData
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: PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly) / 100.0;
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PTEEfficiency = (HostVMEnable == true ? PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly
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/ PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData : 1.0);
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NormalEfficiency = (v->HostVMEnable == true ? v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData
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: v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly) / 100.0;
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PTEEfficiency = (v->HostVMEnable == true ? v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly
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/ v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData : 1.0);
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for (i = 0; i < mode_lib->soc.num_states; ++i) {
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for (j = 0; j <= 1; ++j) {
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double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX] = { 0 };
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@ -6698,58 +6529,58 @@ static void UseMinimumDCFCLK(
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double MinimumTvmPlus2Tr0 = 0;
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TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
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for (k = 0; k < NumberOfActivePlanes; ++k) {
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for (k = 0; k < v->NumberOfActivePlanes; ++k) {
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TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = TotalMaxPrefetchFlipDPTERowBandwidth[i][j]
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+ NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k] / (15.75 * HTotal[k] / PixelClock[k]);
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+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
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}
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for (k = 0; k <= NumberOfActivePlanes - 1; ++k) {
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NoOfDPPState[k] = NoOfDPP[i][j][k];
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for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
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NoOfDPPState[k] = v->NoOfDPP[i][j][k];
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}
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MinimumTWait = CalculateTWait(MaxPrefetchMode, FinalDRAMClockChangeLatency, UrgLatency[i], SREnterPlusExitTime);
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NonDPTEBandwidth = TotalVActivePixelBandwidth[i][j] + TotalVActiveCursorBandwidth[i][j] + TotalMetaRowBandwidth[i][j];
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DPTEBandwidth = (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) ?
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TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : TotalDPTERowBandwidth[i][j];
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DCFCLKRequiredForAverageBandwidth = dml_max3(ProjectedDCFCLKDeepSleep[i][j],
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(NonDPTEBandwidth + TotalDPTERowBandwidth[i][j]) / ReturnBusWidth / (MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation / 100),
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(NonDPTEBandwidth + DPTEBandwidth / PTEEfficiency) / NormalEfficiency / ReturnBusWidth);
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MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime);
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NonDPTEBandwidth = v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j];
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DPTEBandwidth = (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) ?
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TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : v->TotalDPTERowBandwidth[i][j];
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DCFCLKRequiredForAverageBandwidth = dml_max3(v->ProjectedDCFCLKDeepSleep[i][j],
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(NonDPTEBandwidth + v->TotalDPTERowBandwidth[i][j]) / v->ReturnBusWidth / (v->MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation / 100),
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(NonDPTEBandwidth + DPTEBandwidth / PTEEfficiency) / NormalEfficiency / v->ReturnBusWidth);
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ExtraLatencyBytes = CalculateExtraLatencyBytes(ReorderingBytes, TotalNumberOfActiveDPP[i][j], PixelChunkSizeInKByte, TotalNumberOfDCCActiveDPP[i][j],
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MetaChunkSize, GPUVMEnable, HostVMEnable, NumberOfActivePlanes, NoOfDPPState, dpte_group_bytes,
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PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
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HostVMMinPageSize, HostVMMaxNonCachedPageTableLevels);
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ExtraLatencyCycles = RoundTripPingLatencyCycles + 32 + ExtraLatencyBytes / NormalEfficiency / ReturnBusWidth;
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for (k = 0; k < NumberOfActivePlanes; ++k) {
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ExtraLatencyBytes = CalculateExtraLatencyBytes(ReorderingBytes, v->TotalNumberOfActiveDPP[i][j], v->PixelChunkSizeInKByte, v->TotalNumberOfDCCActiveDPP[i][j],
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v->MetaChunkSize, v->GPUVMEnable, v->HostVMEnable, v->NumberOfActivePlanes, NoOfDPPState, v->dpte_group_bytes,
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v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
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v->HostVMMinPageSize, v->HostVMMaxNonCachedPageTableLevels);
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ExtraLatencyCycles = v->RoundTripPingLatencyCycles + 32 + ExtraLatencyBytes / NormalEfficiency / v->ReturnBusWidth;
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for (k = 0; k < v->NumberOfActivePlanes; ++k) {
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double DCFCLKCyclesRequiredInPrefetch = { 0 };
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double ExpectedPrefetchBWAcceleration = { 0 };
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double PrefetchTime = { 0 };
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PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k] * swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k]
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+ PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k] * BytePerPixelC[k]) / NormalEfficiency / ReturnBusWidth;
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DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k] + PDEAndMetaPTEBytesPerFrame[i][j][k] / PTEEfficiency
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/ NormalEfficiency / ReturnBusWidth * (GPUVMMaxPageTableLevels > 2 ? 1 : 0) + 2 * DPTEBytesPerRow[i][j][k] / PTEEfficiency
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/ NormalEfficiency / ReturnBusWidth + 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
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PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k]) * HTotal[k] / PixelClock[k];
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ExpectedPrefetchBWAcceleration = (VActivePixelBandwidth[i][j][k] + VActiveCursorBandwidth[i][j][k]) / (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
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DynamicMetadataVMExtraLatency[k] = (GPUVMEnable == true && DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ?
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UrgLatency[i] * GPUVMMaxPageTableLevels * (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
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PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] - MinimumTWait - UrgLatency[i] * ((GPUVMMaxPageTableLevels <= 2 ? GPUVMMaxPageTableLevels
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: GPUVMMaxPageTableLevels - 2) * (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - DynamicMetadataVMExtraLatency[k];
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PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k]
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+ v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth;
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DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k] + v->PDEAndMetaPTEBytesPerFrame[i][j][k] / PTEEfficiency
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/ NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0) + 2 * v->DPTEBytesPerRow[i][j][k] / PTEEfficiency
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/ NormalEfficiency / v->ReturnBusWidth + 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
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PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
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ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k]) / (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]);
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DynamicMetadataVMExtraLatency[k] = (v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?
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v->UrgLatency[i] * v->GPUVMMaxPageTableLevels * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
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PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - v->UrgLatency[i] * ((v->GPUVMMaxPageTableLevels <= 2 ? v->GPUVMMaxPageTableLevels
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: v->GPUVMMaxPageTableLevels - 2) * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - DynamicMetadataVMExtraLatency[k];
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if (PrefetchTime > 0) {
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double ExpectedVRatioPrefetch = { 0 };
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ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k] / (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
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DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k]
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* dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4) * ExpectedPrefetchBWAcceleration;
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if (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) {
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if (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) {
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DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k]
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+ NoOfDPPState[k] * DPTEBandwidth / PTEEfficiency / NormalEfficiency / ReturnBusWidth;
|
||||
+ NoOfDPPState[k] * DPTEBandwidth / PTEEfficiency / NormalEfficiency / v->ReturnBusWidth;
|
||||
}
|
||||
} else {
|
||||
DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i];
|
||||
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
|
||||
}
|
||||
if (DynamicMetadataEnable[k] == true) {
|
||||
if (v->DynamicMetadataEnable[k] == true) {
|
||||
double TsetupPipe = { 0 };
|
||||
double TdmbfPipe = { 0 };
|
||||
double TdmsksPipe = { 0 };
|
||||
|
|
@ -6757,49 +6588,49 @@ static void UseMinimumDCFCLK(
|
|||
double AllowedTimeForUrgentExtraLatency = { 0 };
|
||||
|
||||
CalculateDynamicMetadataParameters(
|
||||
MaxInterDCNTileRepeaters,
|
||||
RequiredDPPCLK[i][j][k],
|
||||
RequiredDISPCLK[i][j],
|
||||
ProjectedDCFCLKDeepSleep[i][j],
|
||||
PixelClock[k],
|
||||
HTotal[k],
|
||||
VTotal[k] - VActive[k],
|
||||
DynamicMetadataTransmittedBytes[k],
|
||||
DynamicMetadataLinesBeforeActiveRequired[k],
|
||||
Interlace[k],
|
||||
ProgressiveToInterlaceUnitInOPP,
|
||||
v->MaxInterDCNTileRepeaters,
|
||||
v->RequiredDPPCLK[i][j][k],
|
||||
v->RequiredDISPCLK[i][j],
|
||||
v->ProjectedDCFCLKDeepSleep[i][j],
|
||||
v->PixelClock[k],
|
||||
v->HTotal[k],
|
||||
v->VTotal[k] - v->VActive[k],
|
||||
v->DynamicMetadataTransmittedBytes[k],
|
||||
v->DynamicMetadataLinesBeforeActiveRequired[k],
|
||||
v->Interlace[k],
|
||||
v->ProgressiveToInterlaceUnitInOPP,
|
||||
&TsetupPipe,
|
||||
&TdmbfPipe,
|
||||
&TdmecPipe,
|
||||
&TdmsksPipe);
|
||||
AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] / PixelClock[k] - MinimumTWait - TsetupPipe
|
||||
AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TsetupPipe
|
||||
- TdmbfPipe - TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatency[k];
|
||||
if (AllowedTimeForUrgentExtraLatency > 0) {
|
||||
DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(DCFCLKRequiredForPeakBandwidthPerPlane[k],
|
||||
ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency);
|
||||
} else {
|
||||
DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i];
|
||||
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
DCFCLKRequiredForPeakBandwidth = 0;
|
||||
for (k = 0; k <= NumberOfActivePlanes - 1; ++k) {
|
||||
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
|
||||
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
|
||||
}
|
||||
MinimumTvmPlus2Tr0 = UrgLatency[i] * (GPUVMEnable == true ? (HostVMEnable == true ?
|
||||
(GPUVMMaxPageTableLevels + 2) * (HostVMMaxNonCachedPageTableLevels + 1) - 1 : GPUVMMaxPageTableLevels + 1) : 0);
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
MinimumTvmPlus2Tr0 = v->UrgLatency[i] * (v->GPUVMEnable == true ? (v->HostVMEnable == true ?
|
||||
(v->GPUVMMaxPageTableLevels + 2) * (v->HostVMMaxNonCachedPageTableLevels + 1) - 1 : v->GPUVMMaxPageTableLevels + 1) : 0);
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
double MaximumTvmPlus2Tr0PlusTsw = { 0 };
|
||||
MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] / PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
|
||||
MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
|
||||
if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
|
||||
DCFCLKRequiredForPeakBandwidth = DCFCLKPerState[i];
|
||||
DCFCLKRequiredForPeakBandwidth = v->DCFCLKPerState[i];
|
||||
} else {
|
||||
DCFCLKRequiredForPeakBandwidth = dml_max3(DCFCLKRequiredForPeakBandwidth, 2 * ExtraLatencyCycles
|
||||
/ (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4),
|
||||
(2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
|
||||
}
|
||||
}
|
||||
DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 * (1 + mode_lib->vba.PercentMarginOverMinimumRequiredDCFCLK / 100)
|
||||
v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * (1 + mode_lib->vba.PercentMarginOverMinimumRequiredDCFCLK / 100)
|
||||
* dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue