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https://github.com/torvalds/linux
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i2c: add zhaoxin i2c controller driver
Add Zhaoxin I2C controller driver. It provides the access to the i2c busses, which connects to the touchpad, eeprom, I2S, etc. Zhaoxin I2C controller has two separate busses, so may accommodate up to two I2C adapters. Those adapters are listed in the ACPI namespace with the IIC1D17 HID, and probed by a platform driver. The driver works with IRQ mode, and supports basic I2C features. Flags I2C_AQ_NO_ZERO_LEN and I2C_AQ_COMB_WRITE_THEN_READ are used to limit the unsupported access. Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Hans Hu <hanshu-oc@zhaoxin.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
This commit is contained in:
Hans Hu
Andi Shyti
parent
b06204c7d4
commit
a06b80e830
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@ -10258,6 +10258,14 @@ L: linux-i2c@vger.kernel.org
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F: Documentation/i2c/busses/i2c-ismt.rst
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F: drivers/i2c/busses/i2c-ismt.c
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I2C/SMBUS ZHAOXIN DRIVER
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M: Hans Hu <hanshu@zhaoxin.com>
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L: linux-i2c@vger.kernel.org
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S: Maintained
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W: https://www.zhaoxin.com
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F: drivers/i2c/busses/i2c-viai2c-common.c
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F: drivers/i2c/busses/i2c-viai2c-zhaoxin.c
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I2C/SMBUS STUB DRIVER
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M: Jean Delvare <jdelvare@suse.com>
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L: linux-i2c@vger.kernel.org
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@ -344,6 +344,16 @@ config I2C_VIAPRO
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if ACPI
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config I2C_ZHAOXIN
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tristate "Zhaoxin I2C Interface"
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depends on PCI || COMPILE_TEST
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help
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If you say yes to this option, support will be included for the
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ZHAOXIN I2C interface
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This driver can also be built as a module. If so, the module
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will be called i2c-zhaoxin.
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comment "ACPI drivers"
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config I2C_SCMI
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@ -29,6 +29,8 @@ obj-$(CONFIG_I2C_SIS630) += i2c-sis630.o
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obj-$(CONFIG_I2C_SIS96X) += i2c-sis96x.o
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obj-$(CONFIG_I2C_VIA) += i2c-via.o
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obj-$(CONFIG_I2C_VIAPRO) += i2c-viapro.o
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i2c-zhaoxin-objs := i2c-viai2c-zhaoxin.o i2c-viai2c-common.o
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obj-$(CONFIG_I2C_ZHAOXIN) += i2c-zhaoxin.o
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# Mac SMBus host controller drivers
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obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o
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@ -60,7 +60,7 @@ static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last)
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return i2c->ret;
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}
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static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg)
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static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg, bool first)
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{
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u16 val, tcr_val = i2c->tcr;
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@ -81,7 +81,8 @@ static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg)
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writew(tcr_val, i2c->base + VIAI2C_REG_TCR);
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if (i2c->platform == VIAI2C_PLAT_WMT && (pmsg->flags & I2C_M_NOSTART)) {
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if ((i2c->platform == VIAI2C_PLAT_WMT && (pmsg->flags & I2C_M_NOSTART)) ||
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(i2c->platform == VIAI2C_PLAT_ZHAOXIN && !first)) {
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val = readw(i2c->base + VIAI2C_REG_CR);
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val |= VIAI2C_CR_CPU_RDY;
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writew(val, i2c->base + VIAI2C_REG_CR);
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@ -100,6 +101,7 @@ int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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int ret = 0;
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struct viai2c *i2c = i2c_get_adapdata(adap);
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i2c->mode = VIAI2C_BYTE_MODE;
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for (i = 0; ret >= 0 && i < num; i++) {
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pmsg = &msgs[i];
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if (i2c->platform == VIAI2C_PLAT_WMT && !(pmsg->flags & I2C_M_NOSTART)) {
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@ -112,7 +114,7 @@ int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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i2c->xfered_len = 0;
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if (pmsg->flags & I2C_M_RD)
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ret = viai2c_read(i2c, pmsg);
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ret = viai2c_read(i2c, pmsg, i == 0);
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else
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ret = viai2c_write(i2c, pmsg, (i + 1) == num);
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}
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@ -157,6 +159,8 @@ static int viai2c_irq_xfer(struct viai2c *i2c)
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if ((i2c->xfered_len + 1) == msg->len) {
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if (i2c->platform == VIAI2C_PLAT_WMT && !i2c->last)
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writew(VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR);
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else if (i2c->platform == VIAI2C_PLAT_ZHAOXIN && i2c->last)
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writeb(VIAI2C_CR_TX_END, base + VIAI2C_REG_CR);
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} else {
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writew(msg->buf[i2c->xfered_len + 1] & 0xFF, base + VIAI2C_REG_CDR);
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writew(VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR);
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@ -168,6 +172,11 @@ static int viai2c_irq_xfer(struct viai2c *i2c)
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return i2c->xfered_len == msg->len;
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}
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int __weak viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq)
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{
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return 0;
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}
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static irqreturn_t viai2c_isr(int irq, void *data)
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{
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struct viai2c *i2c = data;
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@ -175,6 +184,9 @@ static irqreturn_t viai2c_isr(int irq, void *data)
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/* save the status and write-clear it */
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status = readw(i2c->base + VIAI2C_REG_ISR);
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if (!status && i2c->platform == VIAI2C_PLAT_ZHAOXIN)
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return IRQ_NONE;
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writew(status, i2c->base + VIAI2C_REG_ISR);
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i2c->ret = 0;
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@ -184,8 +196,12 @@ static irqreturn_t viai2c_isr(int irq, void *data)
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if (i2c->platform == VIAI2C_PLAT_WMT && (status & VIAI2C_ISR_SCL_TIMEOUT))
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i2c->ret = -ETIMEDOUT;
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if (!i2c->ret)
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i2c->ret = viai2c_irq_xfer(i2c);
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if (!i2c->ret) {
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if (i2c->mode == VIAI2C_BYTE_MODE)
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i2c->ret = viai2c_irq_xfer(i2c);
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else
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i2c->ret = viai2c_fifo_irq_xfer(i2c, true);
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}
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/* All the data has been successfully transferred or error occurred */
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if (i2c->ret)
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@ -214,6 +230,11 @@ int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat)
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i2c->irq = irq_of_parse_and_map(np, 0);
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if (!i2c->irq)
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return -EINVAL;
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} else if (plat == VIAI2C_PLAT_ZHAOXIN) {
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irq_flags = IRQF_SHARED;
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i2c->irq = platform_get_irq(pdev, 0);
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if (i2c->irq < 0)
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return i2c->irq;
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} else {
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return dev_err_probe(&pdev->dev, -EINVAL, "wrong platform type\n");
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}
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@ -52,6 +52,12 @@
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enum {
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VIAI2C_PLAT_WMT,
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VIAI2C_PLAT_ZHAOXIN
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};
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enum {
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VIAI2C_BYTE_MODE,
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VIAI2C_FIFO_MODE
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};
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struct viai2c {
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@ -66,11 +72,14 @@ struct viai2c {
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struct i2c_msg *msg;
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int ret;
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bool last;
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unsigned int mode;
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unsigned int platform;
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void *pltfm_priv;
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};
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int viai2c_wait_bus_not_busy(struct viai2c *i2c);
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int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num);
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int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat);
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int viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq);
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#endif
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298
drivers/i2c/busses/i2c-viai2c-zhaoxin.c
Normal file
298
drivers/i2c/busses/i2c-viai2c-zhaoxin.c
Normal file
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@ -0,0 +1,298 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright(c) 2024 Shanghai Zhaoxin Semiconductor Corporation.
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* All rights reserved.
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*/
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#include <linux/acpi.h>
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#include "i2c-viai2c-common.h"
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/*
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* registers
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*/
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/* Zhaoxin specific register bit fields */
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/* REG_CR Bit fields */
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#define ZXI2C_CR_MST_RST BIT(7)
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#define ZXI2C_CR_FIFO_MODE BIT(14)
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/* REG_ISR/IMR Bit fields */
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#define ZXI2C_IRQ_FIFONACK BIT(4)
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#define ZXI2C_IRQ_FIFOEND BIT(3)
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#define ZXI2C_IRQ_MASK (VIAI2C_ISR_MASK_ALL \
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| ZXI2C_IRQ_FIFOEND \
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| ZXI2C_IRQ_FIFONACK)
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/* Zhaoxin specific registers */
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#define ZXI2C_REG_CLK 0x10
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#define ZXI2C_CLK_50M BIT(0)
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#define ZXI2C_REG_REV 0x11
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#define ZXI2C_REG_HCR 0x12
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#define ZXI2C_HCR_RST_FIFO GENMASK(1, 0)
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#define ZXI2C_REG_HTDR 0x13
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#define ZXI2C_REG_HRDR 0x14
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#define ZXI2C_REG_HTLR 0x15
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#define ZXI2C_REG_HRLR 0x16
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#define ZXI2C_REG_HWCNTR 0x18
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#define ZXI2C_REG_HRCNTR 0x19
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/* parameters Constants */
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#define ZXI2C_GOLD_FSTP_100K 0xF3
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#define ZXI2C_GOLD_FSTP_400K 0x38
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#define ZXI2C_GOLD_FSTP_1M 0x13
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#define ZXI2C_GOLD_FSTP_3400K 0x37
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#define ZXI2C_HS_MASTER_CODE (0x08 << 8)
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#define ZXI2C_FIFO_SIZE 32
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struct viai2c_zhaoxin {
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u8 hrv;
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u16 tr;
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u16 mcr;
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u16 xfer_len;
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};
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/* 'irq == true' means in interrupt context */
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int viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq)
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{
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u16 i;
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u8 tmp;
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struct i2c_msg *msg = i2c->msg;
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void __iomem *base = i2c->base;
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bool read = !!(msg->flags & I2C_M_RD);
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struct viai2c_zhaoxin *priv = i2c->pltfm_priv;
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if (irq) {
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/* get the received data */
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if (read)
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for (i = 0; i < priv->xfer_len; i++)
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msg->buf[i2c->xfered_len + i] = ioread8(base + ZXI2C_REG_HRDR);
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i2c->xfered_len += priv->xfer_len;
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if (i2c->xfered_len == msg->len)
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return 1;
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}
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/* reset fifo buffer */
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tmp = ioread8(base + ZXI2C_REG_HCR);
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iowrite8(tmp | ZXI2C_HCR_RST_FIFO, base + ZXI2C_REG_HCR);
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/* set xfer len */
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priv->xfer_len = min_t(u16, msg->len - i2c->xfered_len, ZXI2C_FIFO_SIZE);
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if (read) {
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iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HRLR);
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} else {
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iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HTLR);
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/* set write data */
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for (i = 0; i < priv->xfer_len; i++)
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iowrite8(msg->buf[i2c->xfered_len + i], base + ZXI2C_REG_HTDR);
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}
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/* prepare to stop transmission */
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if (priv->hrv && msg->len == (i2c->xfered_len + priv->xfer_len)) {
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tmp = ioread8(base + VIAI2C_REG_CR);
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tmp |= read ? VIAI2C_CR_RX_END : VIAI2C_CR_TX_END;
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iowrite8(tmp, base + VIAI2C_REG_CR);
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}
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if (irq) {
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/* continue transmission */
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tmp = ioread8(base + VIAI2C_REG_CR);
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iowrite8(tmp |= VIAI2C_CR_CPU_RDY, base + VIAI2C_REG_CR);
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} else {
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u16 tcr_val = i2c->tcr;
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/* start transmission */
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tcr_val |= read ? VIAI2C_TCR_READ : 0;
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writew(tcr_val | msg->addr, base + VIAI2C_REG_TCR);
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}
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return 0;
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}
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static int zxi2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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{
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u8 tmp;
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int ret;
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struct viai2c *i2c = (struct viai2c *)i2c_get_adapdata(adap);
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struct viai2c_zhaoxin *priv = i2c->pltfm_priv;
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void __iomem *base = i2c->base;
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ret = viai2c_wait_bus_not_busy(i2c);
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if (ret)
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return ret;
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tmp = ioread8(base + VIAI2C_REG_CR);
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tmp &= ~(VIAI2C_CR_RX_END | VIAI2C_CR_TX_END);
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if (num == 1 && msgs->len >= 2 && (priv->hrv || msgs->len <= ZXI2C_FIFO_SIZE)) {
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/* enable fifo mode */
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iowrite16(ZXI2C_CR_FIFO_MODE | tmp, base + VIAI2C_REG_CR);
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/* clear irq status */
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iowrite8(ZXI2C_IRQ_MASK, base + VIAI2C_REG_ISR);
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/* enable fifo irq */
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iowrite8(VIAI2C_ISR_NACK_ADDR | ZXI2C_IRQ_FIFOEND, base + VIAI2C_REG_IMR);
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i2c->msg = msgs;
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i2c->mode = VIAI2C_FIFO_MODE;
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priv->xfer_len = 0;
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i2c->xfered_len = 0;
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viai2c_fifo_irq_xfer(i2c, 0);
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if (!wait_for_completion_timeout(&i2c->complete, VIAI2C_TIMEOUT))
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return -ETIMEDOUT;
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ret = i2c->ret;
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} else {
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/* enable byte mode */
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iowrite16(tmp, base + VIAI2C_REG_CR);
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/* clear irq status */
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iowrite8(ZXI2C_IRQ_MASK, base + VIAI2C_REG_ISR);
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/* enable byte irq */
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iowrite8(VIAI2C_ISR_NACK_ADDR | VIAI2C_IMR_BYTE, base + VIAI2C_REG_IMR);
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ret = viai2c_xfer(adap, msgs, num);
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if (ret == -ETIMEDOUT)
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iowrite16(tmp | VIAI2C_CR_END_MASK, base + VIAI2C_REG_CR);
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}
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/* dis interrupt */
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iowrite8(0, base + VIAI2C_REG_IMR);
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return ret;
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}
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static u32 zxi2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm zxi2c_algorithm = {
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.master_xfer = zxi2c_master_xfer,
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.functionality = zxi2c_func,
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};
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static const struct i2c_adapter_quirks zxi2c_quirks = {
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.flags = I2C_AQ_NO_ZERO_LEN | I2C_AQ_COMB_WRITE_THEN_READ,
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};
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static const u32 zxi2c_speed_params_table[][3] = {
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/* speed, ZXI2C_TCR, ZXI2C_FSTP */
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{ I2C_MAX_STANDARD_MODE_FREQ, 0, ZXI2C_GOLD_FSTP_100K },
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{ I2C_MAX_FAST_MODE_FREQ, VIAI2C_TCR_FAST, ZXI2C_GOLD_FSTP_400K },
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{ I2C_MAX_FAST_MODE_PLUS_FREQ, VIAI2C_TCR_FAST, ZXI2C_GOLD_FSTP_1M },
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{ I2C_MAX_HIGH_SPEED_MODE_FREQ, VIAI2C_TCR_HS_MODE | VIAI2C_TCR_FAST,
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ZXI2C_GOLD_FSTP_3400K },
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};
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static void zxi2c_set_bus_speed(struct viai2c *i2c)
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{
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struct viai2c_zhaoxin *priv = i2c->pltfm_priv;
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iowrite16(priv->tr, i2c->base + VIAI2C_REG_TR);
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iowrite8(ZXI2C_CLK_50M, i2c->base + ZXI2C_REG_CLK);
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iowrite16(priv->mcr, i2c->base + VIAI2C_REG_MCR);
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}
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|
||||
static void zxi2c_get_bus_speed(struct viai2c *i2c)
|
||||
{
|
||||
u8 i, count;
|
||||
u8 fstp;
|
||||
const u32 *params;
|
||||
struct viai2c_zhaoxin *priv = i2c->pltfm_priv;
|
||||
u32 acpi_speed = i2c_acpi_find_bus_speed(i2c->dev);
|
||||
|
||||
count = ARRAY_SIZE(zxi2c_speed_params_table);
|
||||
for (i = 0; i < count; i++)
|
||||
if (acpi_speed == zxi2c_speed_params_table[i][0])
|
||||
break;
|
||||
/* if not found, use 400k as default */
|
||||
i = i < count ? i : 1;
|
||||
|
||||
params = zxi2c_speed_params_table[i];
|
||||
fstp = ioread8(i2c->base + VIAI2C_REG_TR);
|
||||
if (abs(fstp - params[2]) > 0x10) {
|
||||
/*
|
||||
* if BIOS setting value far from golden value,
|
||||
* use golden value and warn user
|
||||
*/
|
||||
dev_warn(i2c->dev, "FW FSTP[%x] might cause wrong timings, dropped\n", fstp);
|
||||
priv->tr = params[2] | 0xff00;
|
||||
} else {
|
||||
priv->tr = fstp | 0xff00;
|
||||
}
|
||||
|
||||
i2c->tcr = params[1];
|
||||
priv->mcr = ioread16(i2c->base + VIAI2C_REG_MCR);
|
||||
/* for Hs-mode, use 0x80 as master code */
|
||||
if (params[0] == I2C_MAX_HIGH_SPEED_MODE_FREQ)
|
||||
priv->mcr |= ZXI2C_HS_MASTER_CODE;
|
||||
|
||||
dev_info(i2c->dev, "speed mode is %s\n", i2c_freq_mode_string(params[0]));
|
||||
}
|
||||
|
||||
static int zxi2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
int error;
|
||||
struct viai2c *i2c;
|
||||
struct i2c_adapter *adap;
|
||||
struct viai2c_zhaoxin *priv;
|
||||
|
||||
error = viai2c_init(pdev, &i2c, VIAI2C_PLAT_ZHAOXIN);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
i2c->pltfm_priv = priv;
|
||||
|
||||
zxi2c_get_bus_speed(i2c);
|
||||
zxi2c_set_bus_speed(i2c);
|
||||
|
||||
priv->hrv = ioread8(i2c->base + ZXI2C_REG_REV);
|
||||
|
||||
adap = &i2c->adapter;
|
||||
adap->owner = THIS_MODULE;
|
||||
adap->algo = &zxi2c_algorithm;
|
||||
adap->quirks = &zxi2c_quirks;
|
||||
adap->dev.parent = &pdev->dev;
|
||||
ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
|
||||
snprintf(adap->name, sizeof(adap->name), "zhaoxin-%s-%s",
|
||||
dev_name(pdev->dev.parent), dev_name(i2c->dev));
|
||||
i2c_set_adapdata(adap, i2c);
|
||||
|
||||
return devm_i2c_add_adapter(&pdev->dev, adap);
|
||||
}
|
||||
|
||||
static int __maybe_unused zxi2c_resume(struct device *dev)
|
||||
{
|
||||
struct viai2c *i2c = dev_get_drvdata(dev);
|
||||
|
||||
iowrite8(ZXI2C_CR_MST_RST, i2c->base + VIAI2C_REG_CR);
|
||||
zxi2c_set_bus_speed(i2c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops zxi2c_pm = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(NULL, zxi2c_resume)
|
||||
};
|
||||
|
||||
static const struct acpi_device_id zxi2c_acpi_match[] = {
|
||||
{"IIC1D17", 0 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, zxi2c_acpi_match);
|
||||
|
||||
static struct platform_driver zxi2c_driver = {
|
||||
.probe = zxi2c_probe,
|
||||
.driver = {
|
||||
.name = "i2c_zhaoxin",
|
||||
.acpi_match_table = zxi2c_acpi_match,
|
||||
.pm = &zxi2c_pm,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(zxi2c_driver);
|
||||
|
||||
MODULE_AUTHOR("HansHu@zhaoxin.com");
|
||||
MODULE_DESCRIPTION("Shanghai Zhaoxin IIC driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in a new issue