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[MIPS] Add GENERIC_HARDIRQS_NO__DO_IRQ for i8259 users
Now that i8259A_chip uses new irq flow handler select GENERIC_HARDIRQS_NO__DO_IRQ on some more platforms. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -165,6 +165,7 @@ config MIPS_COBALT
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select GENERIC_HARDIRQS_NO__DO_IRQ
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config MACH_DECSTATION
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bool "DECstations"
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@ -225,6 +226,7 @@ config MACH_JAZZ
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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select SYS_SUPPORTS_100HZ
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select GENERIC_HARDIRQS_NO__DO_IRQ
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help
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This a family of machines based on the MIPS R4030 chipset which was
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used by several vendors to build RISC/os and Windows NT workstations.
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@ -482,6 +484,7 @@ config MACH_VR41XX
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select SYS_HAS_CPU_VR41XX
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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select GENERIC_HARDIRQS_NO__DO_IRQ
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config PMC_YOSEMITE
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bool "PMC-Sierra Yosemite eval board"
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@ -515,6 +518,7 @@ config QEMU
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select ARCH_SPARSEMEM_ENABLE
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select GENERIC_HARDIRQS_NO__DO_IRQ
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help
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Qemu is a software emulator which among other architectures also
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can simulate a MIPS32 4Kc system. This patch adds support for the
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@ -754,6 +758,7 @@ config TOSHIBA_RBTX4927
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select TOSHIBA_BOARDS
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select GENERIC_HARDIRQS_NO__DO_IRQ
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help
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This Toshiba board is based on the TX4927 processor. Say Y here to
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support this machine type
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@ -773,6 +778,7 @@ config TOSHIBA_RBTX4938
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_BIG_ENDIAN
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select TOSHIBA_BOARDS
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select GENERIC_HARDIRQS_NO__DO_IRQ
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help
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This Toshiba board is based on the TX4938 processor. Say Y here to
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support this machine type
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@ -158,7 +158,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
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#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
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#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
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#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
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#define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ( 1 << 26 )
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#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
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#endif
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@ -175,7 +174,6 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
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// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
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// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
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// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
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// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
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);
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#endif
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@ -226,7 +224,6 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
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static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
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static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
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static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
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static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
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#endif
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#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
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@ -249,7 +246,6 @@ static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
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.mask = toshiba_rbtx4927_irq_isa_disable,
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.mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
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.unmask = toshiba_rbtx4927_irq_isa_enable,
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.end = toshiba_rbtx4927_irq_isa_end,
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};
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#endif
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@ -402,7 +398,8 @@ static void __init toshiba_rbtx4927_irq_isa_init(void)
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for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
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i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
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set_irq_chip(i, &toshiba_rbtx4927_irq_isa_type);
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set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_isa_type,
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handle_level_irq);
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setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
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&toshiba_rbtx4927_irq_isa_master);
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@ -470,26 +467,6 @@ static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
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#endif
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#ifdef CONFIG_TOSHIBA_FPCIB0
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static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
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{
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TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ,
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"irq=%d\n", irq);
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if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
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|| irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
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TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
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"bad irq=%d\n", irq);
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panic("\n");
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}
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
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toshiba_rbtx4927_irq_isa_enable(irq);
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}
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}
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#endif
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void __init arch_init_irq(void)
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{
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extern void tx4927_irq_init(void);
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@ -6,7 +6,6 @@ config CASIO_E55
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select ISA
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select GENERIC_HARDIRQS_NO__DO_IRQ
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config IBM_WORKPAD
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bool "Support for IBM WorkPad z50"
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@ -16,7 +15,6 @@ config IBM_WORKPAD
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select ISA
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select GENERIC_HARDIRQS_NO__DO_IRQ
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config NEC_CMBVR4133
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bool "Support for NEC CMB-VR4133"
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@ -41,7 +39,6 @@ config TANBAC_TB022X
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select IRQ_CPU
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select GENERIC_HARDIRQS_NO__DO_IRQ
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help
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The TANBAC VR4131 multichip module(TB0225) and
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the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms
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@ -74,7 +71,6 @@ config VICTOR_MPC30X
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select IRQ_CPU
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select GENERIC_HARDIRQS_NO__DO_IRQ
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config ZAO_CAPCELLA
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bool "Support for ZAO Networks Capcella"
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@ -84,7 +80,6 @@ config ZAO_CAPCELLA
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select IRQ_CPU
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select GENERIC_HARDIRQS_NO__DO_IRQ
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config PCI_VR41XX
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bool "Add PCI control unit support of NEC VR4100 series"
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@ -45,19 +45,12 @@ static void ack_i8259_irq(unsigned int irq)
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mask_and_ack_8259A(irq - I8259_IRQ_BASE);
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}
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static void end_i8259_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_8259A_irq(irq - I8259_IRQ_BASE);
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}
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static struct irq_chip i8259_irq_type = {
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.typename = "XT-PIC",
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.ack = ack_i8259_irq,
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.mask = disable_i8259_irq,
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.mask_ack = ack_i8259_irq,
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.unmask = enable_i8259_irq,
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.end = end_i8259_irq,
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};
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static int i8259_get_irq_number(int irq)
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@ -92,7 +85,7 @@ void __init rockhopper_init_irq(void)
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}
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for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++)
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set_irq_chip(i, &i8259_irq_type);
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set_irq_chip_and_handler(i, &i8259_irq_type, handle_level_irq);
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setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade);
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