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drm/omap: hdmi5: automatically choose limited/full range output
Currently the HDMI driver uses always limited range RGB output. This patch improves the behavior by using limited range only if the output is identified as a HDMI display, and VIC > 1. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190930103840.18970-7-tomi.valkeinen@ti.com
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@ -23,18 +23,6 @@
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#include "hdmi5_core.h"
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/* only 24 bit color depth used for now */
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static const struct csc_table csc_table_deepcolor[] = {
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/* HDMI_DEEP_COLOR_24BIT */
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[0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
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/* HDMI_DEEP_COLOR_30BIT */
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[1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
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/* HDMI_DEEP_COLOR_36BIT */
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[2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
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/* FULL RANGE */
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[3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
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};
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static void hdmi_core_ddc_init(struct hdmi_core_data *core)
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{
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void __iomem *base = core->base;
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@ -397,14 +385,6 @@ static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
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REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
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}
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static void hdmi_core_config_csc(struct hdmi_core_data *core)
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{
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int clr_depth = 0; /* 24 bit color depth */
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/* CSC_COLORDEPTH */
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REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
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}
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static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
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{
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int video_mapping = 1; /* for 24 bit color depth */
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@ -469,47 +449,67 @@ static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
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REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
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}
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static void hdmi_core_csc_config(struct hdmi_core_data *core,
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struct csc_table csc_coeff)
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static void hdmi_core_write_csc(struct hdmi_core_data *core,
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const struct csc_table *csc_coeff)
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{
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void __iomem *base = core->base;
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff->a1 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff->a1, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff->a2 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff->a2, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff->a3 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff->a3, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff->a4 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff->a4, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff->b1 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff->b1, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff->b2 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff->b2, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff->b3 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff->b3, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff->b4 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff->b4, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff->c1 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff->c1, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff->c2 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff->c2, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff->c3 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff->c3, 7, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff->c4 >> 8, 6, 0);
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REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff->c4, 7, 0);
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/* enable CSC */
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REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
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}
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static void hdmi_core_configure_range(struct hdmi_core_data *core)
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static void hdmi_core_configure_range(struct hdmi_core_data *core,
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enum hdmi_quantization_range range)
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{
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struct csc_table csc_coeff = { 0 };
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static const struct csc_table csc_limited_range = {
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7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32
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};
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static const struct csc_table csc_full_range = {
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8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0
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};
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const struct csc_table *csc_coeff;
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/* support limited range with 24 bit color depth for now */
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csc_coeff = csc_table_deepcolor[0];
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/* CSC_COLORDEPTH = 24 bits*/
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REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, 0, 7, 4);
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hdmi_core_csc_config(core, csc_coeff);
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switch (range) {
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case HDMI_QUANTIZATION_RANGE_FULL:
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csc_coeff = &csc_full_range;
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break;
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case HDMI_QUANTIZATION_RANGE_DEFAULT:
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case HDMI_QUANTIZATION_RANGE_LIMITED:
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default:
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csc_coeff = &csc_limited_range;
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break;
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}
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hdmi_core_write_csc(core, csc_coeff);
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}
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static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
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@ -600,9 +600,20 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
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struct videomode vm;
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struct hdmi_video_format video_format;
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struct hdmi_core_vid_config v_core_cfg;
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enum hdmi_quantization_range range;
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hdmi_core_mask_interrupts(core);
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if (cfg->hdmi_dvi_mode == HDMI_HDMI) {
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char vic = cfg->infoframe.video_code;
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/* All CEA modes other than VIC 1 use limited quantization range. */
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range = vic > 1 ? HDMI_QUANTIZATION_RANGE_LIMITED :
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HDMI_QUANTIZATION_RANGE_FULL;
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} else {
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range = HDMI_QUANTIZATION_RANGE_FULL;
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}
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hdmi_core_init(&v_core_cfg, cfg);
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hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
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@ -616,9 +627,8 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
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hdmi_wp_video_config_interface(wp, &vm);
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/* support limited range with 24 bit color depth for now */
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hdmi_core_configure_range(core);
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cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
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hdmi_core_configure_range(core, range);
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cfg->infoframe.quantization_range = range;
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/*
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* configure core video part, set software reset in the core
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@ -628,7 +638,6 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
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hdmi_core_video_config(core, &v_core_cfg);
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hdmi_core_config_video_packetizer(core);
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hdmi_core_config_csc(core);
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hdmi_core_config_video_sampler(core);
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if (cfg->hdmi_dvi_mode == HDMI_HDMI)
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