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https://github.com/torvalds/linux
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Qualcomm ARM Based SoC Updates for v3.20-2
* Various bug fixes and minor feature additions to scm code * Added big-endian support to debug MSM uart * Added big-endian support to ARCH_QCOM * Cleaned up some Kconfig options associated with ARCH_QCOM * Added Andy Gross as co-maintainer -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: GPGTools - https://gpgtools.org iQIcBAABCgAGBQJUwneSAAoJEF9hYXeAcXzBSMQQAKoE7TK1gHTxXZrZNGvNOLgi v8Dy/jWV07pnMA41JDyW+IgEi8C7X7Byax6G6kCyKHVOk9TkDN3zS4XTxJWGVKa2 0f4QIJcStoHNXvUWe6rYGoW1nOyOae38uCWDY8dY+4x3gaOC3oV34NDmOlVEN5Gi KL0H90pHf8XLlKfx9rblkQT87Cxm/Y76xi0pnCHSyIuxsmAGInXT4zvRb/j4P1lJ 9IEWcp6kELqa2afn/OcXdsWFlvsc/BvMeXq1yl1nFawyfkpItX98wYTZGp9yuz8c MRKp8Ph3lgjvHbA6EME5mumg2/uhLvv+Klbl24bNwHVfxvDyUZwEHdSOFWTboKZW lfY+oe5hiwL68WYruBDqyziYjhe7kTX1/Iw0K/NHn0aWsng52CW/i0GjAaefxl6i FFV3+39vZh1bUNmynX69zPoRSKmB16ibFaTUl4Z7AoGqxq7rM8wRXP7xizAwuULK q8mCAVLEBgtAzqa2T8inM+USbL4K/qnzPEQzPG7Z6JxG05U2t+Huw2YD25wavIhE yvvfxkMli0fojRjp9CI/MbeloA3h0dRdc3zCMF5qkgAjRK4ozQVZ4BhDWn7jCC8/ QTCKxsYj977k6BUdHLTN3Z7/iW7F2HHXQRiJ9+HXLeLiTOSksFXnc2buHD6lwiRI mO6avae7XSGMpNYLa1RB =04jb -----END PGP SIGNATURE----- Merge tag 'qcom-soc-for-3.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/soc merge "qcom SoC changes for v3.20-2" from Kumar Gala: Qualcomm ARM Based SoC Updates for v3.20-2 * Various bug fixes and minor feature additions to scm code * Added big-endian support to debug MSM uart * Added big-endian support to ARCH_QCOM * Cleaned up some Kconfig options associated with ARCH_QCOM * Added Andy Gross as co-maintainer * tag 'qcom-soc-for-3.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: MAINTAINERS: Add co-maintainer for ARM/Qualcomm Support ARM: qcom: Drop unnecessary selects from ARCH_QCOM ARM: qcom: Fix SCM interface for big-endian kernels ARM: qcom: scm: Clarify boot interface ARM: qcom: Add SCM warmboot flags for quad core targets. ARM: qcom: scm: Add logging of actual return code from scm call ARM: qcom: scm: Flush the command buffer only instead of the entire cache ARM: qcom: scm: Get cacheline size from CTR ARM: qcom: scm: Fix incorrect cache invalidation ARM: qcom: Select ARCH_SUPPORTS_BIG_ENDIAN ARM: debug: msm: Support big-endian CPUs ARM: debug: Update MSM and QCOM DEBUG_LL help Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
9b865d9b5c
7 changed files with 77 additions and 39 deletions
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@ -1291,10 +1291,13 @@ S: Maintained
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ARM/QUALCOMM SUPPORT
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M: Kumar Gala <galak@codeaurora.org>
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M: Andy Gross <agross@codeaurora.org>
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M: David Brown <davidb@codeaurora.org>
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L: linux-arm-msm@vger.kernel.org
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L: linux-soc@vger.kernel.org
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S: Maintained
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F: arch/arm/mach-qcom/
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F: drivers/soc/qcom/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
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ARM/RADISYS ENP2611 MACHINE SUPPORT
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@ -438,7 +438,7 @@ choice
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Say Y here if you want the debug print routines to direct
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their output to the serial port on MSM devices.
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ARCH DEBUG_UART_PHYS DEBUG_UART_BASE #
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ARCH DEBUG_UART_PHYS DEBUG_UART_VIRT #
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MSM7X00A, QSD8X50 0xa9a00000 0xe1000000 UART1
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MSM7X00A, QSD8X50 0xa9b00000 0xe1000000 UART2
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MSM7X00A, QSD8X50 0xa9c00000 0xe1000000 UART3
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@ -457,7 +457,8 @@ choice
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Say Y here if you want the debug print routines to direct
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their output to the serial port on Qualcomm devices.
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ARCH DEBUG_UART_PHYS DEBUG_UART_BASE
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ARCH DEBUG_UART_PHYS DEBUG_UART_VIRT
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APQ8064 0x16640000 0xf0040000
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APQ8084 0xf995e000 0xfa75e000
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MSM8X60 0x19c40000 0xf0040000
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MSM8960 0x16440000 0xf0040000
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@ -23,6 +23,7 @@
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.endm
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.macro senduart, rd, rx
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ARM_BE8(rev \rd, \rd )
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#ifdef CONFIG_DEBUG_QCOM_UARTDM
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@ Write the 1 character to UARTDM_TF
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str \rd, [\rx, #0x70]
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@ -35,24 +36,29 @@
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#ifdef CONFIG_DEBUG_QCOM_UARTDM
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@ check for TX_EMT in UARTDM_SR
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ldr \rd, [\rx, #0x08]
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ARM_BE8(rev \rd, \rd )
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tst \rd, #0x08
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bne 1002f
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@ wait for TXREADY in UARTDM_ISR
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1001: ldr \rd, [\rx, #0x14]
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ARM_BE8(rev \rd, \rd )
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tst \rd, #0x80
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beq 1001b
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1002:
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@ Clear TX_READY by writing to the UARTDM_CR register
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mov \rd, #0x300
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ARM_BE8(rev \rd, \rd )
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str \rd, [\rx, #0x10]
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@ Write 0x1 to NCF register
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mov \rd, #0x1
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ARM_BE8(rev \rd, \rd )
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str \rd, [\rx, #0x40]
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@ UARTDM reg. Read to induce delay
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ldr \rd, [\rx, #0x08]
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#else
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@ wait for TX_READY
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1001: ldr \rd, [\rx, #0x08]
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ARM_BE8(rev \rd, \rd )
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tst \rd, #0x04
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beq 1001b
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#endif
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@ -1,9 +1,8 @@
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menuconfig ARCH_QCOM
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bool "Qualcomm Support" if ARCH_MULTI_V7
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_SUPPORTS_BIG_ENDIAN
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select ARM_GIC
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select ARM_AMBA
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select CLKSRC_OF
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select PINCTRL
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select QCOM_SCM if SMP
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help
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@ -24,15 +24,15 @@
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/*
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* Set the cold/warm boot address for one of the CPU cores.
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*/
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int scm_set_boot_addr(phys_addr_t addr, int flags)
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int scm_set_boot_addr(u32 addr, int flags)
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{
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struct {
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unsigned int flags;
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phys_addr_t addr;
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__le32 flags;
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__le32 addr;
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} cmd;
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cmd.addr = addr;
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cmd.flags = flags;
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cmd.addr = cpu_to_le32(addr);
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cmd.flags = cpu_to_le32(flags);
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return scm_call(SCM_SVC_BOOT, SCM_BOOT_ADDR,
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&cmd, sizeof(cmd), NULL, 0);
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}
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@ -18,7 +18,9 @@
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#define SCM_FLAG_COLDBOOT_CPU3 0x20
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#define SCM_FLAG_WARMBOOT_CPU0 0x04
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#define SCM_FLAG_WARMBOOT_CPU1 0x02
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#define SCM_FLAG_WARMBOOT_CPU2 0x10
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#define SCM_FLAG_WARMBOOT_CPU3 0x40
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int scm_set_boot_addr(phys_addr_t addr, int flags);
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int scm_set_boot_addr(u32 addr, int flags);
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#endif
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@ -22,13 +22,11 @@
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <asm/outercache.h>
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#include <asm/cacheflush.h>
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#include "scm.h"
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/* Cache line size for msm8x60 */
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#define CACHELINESIZE 32
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#define SCM_ENOMEM -5
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#define SCM_EOPNOTSUPP -4
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#define SCM_EINVAL_ADDR -3
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@ -63,11 +61,11 @@ static DEFINE_MUTEX(scm_lock);
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* to access the buffers in a safe manner.
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*/
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struct scm_command {
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u32 len;
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u32 buf_offset;
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u32 resp_hdr_offset;
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u32 id;
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u32 buf[0];
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__le32 len;
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__le32 buf_offset;
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__le32 resp_hdr_offset;
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__le32 id;
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__le32 buf[0];
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};
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/**
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@ -77,9 +75,9 @@ struct scm_command {
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* @is_complete: indicates if the command has finished processing
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*/
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struct scm_response {
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u32 len;
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u32 buf_offset;
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u32 is_complete;
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__le32 len;
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__le32 buf_offset;
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__le32 is_complete;
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};
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/**
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@ -97,12 +95,14 @@ static struct scm_command *alloc_scm_command(size_t cmd_size, size_t resp_size)
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struct scm_command *cmd;
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size_t len = sizeof(*cmd) + sizeof(struct scm_response) + cmd_size +
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resp_size;
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u32 offset;
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cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL);
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if (cmd) {
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cmd->len = len;
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cmd->buf_offset = offsetof(struct scm_command, buf);
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cmd->resp_hdr_offset = cmd->buf_offset + cmd_size;
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cmd->len = cpu_to_le32(len);
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offset = offsetof(struct scm_command, buf);
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cmd->buf_offset = cpu_to_le32(offset);
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cmd->resp_hdr_offset = cpu_to_le32(offset + cmd_size);
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}
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return cmd;
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}
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@ -127,7 +127,7 @@ static inline void free_scm_command(struct scm_command *cmd)
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static inline struct scm_response *scm_command_to_response(
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const struct scm_command *cmd)
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{
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return (void *)cmd + cmd->resp_hdr_offset;
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return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
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}
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/**
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@ -149,11 +149,12 @@ static inline void *scm_get_command_buffer(const struct scm_command *cmd)
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*/
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static inline void *scm_get_response_buffer(const struct scm_response *rsp)
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{
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return (void *)rsp + rsp->buf_offset;
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return (void *)rsp + le32_to_cpu(rsp->buf_offset);
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}
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static int scm_remap_error(int err)
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{
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pr_err("scm_call failed with error code %d\n", err);
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switch (err) {
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case SCM_ERROR:
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return -EIO;
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@ -198,11 +199,12 @@ static int __scm_call(const struct scm_command *cmd)
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u32 cmd_addr = virt_to_phys(cmd);
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/*
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* Flush the entire cache here so callers don't have to remember
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* to flush the cache when passing physical addresses to the secure
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* side in the buffer.
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* Flush the command buffer so that the secure world sees
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* the correct data.
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*/
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flush_cache_all();
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__cpuc_flush_dcache_area((void *)cmd, cmd->len);
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outer_flush_range(cmd_addr, cmd_addr + cmd->len);
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ret = smc(cmd_addr);
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if (ret < 0)
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ret = scm_remap_error(ret);
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@ -210,6 +212,25 @@ static int __scm_call(const struct scm_command *cmd)
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return ret;
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}
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static void scm_inv_range(unsigned long start, unsigned long end)
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{
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u32 cacheline_size, ctr;
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asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
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cacheline_size = 4 << ((ctr >> 16) & 0xf);
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start = round_down(start, cacheline_size);
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end = round_up(end, cacheline_size);
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outer_inv_range(start, end);
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while (start < end) {
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asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
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: "memory");
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start += cacheline_size;
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}
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dsb();
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isb();
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}
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/**
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* scm_call() - Send an SCM command
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* @svc_id: service identifier
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@ -220,6 +241,13 @@ static int __scm_call(const struct scm_command *cmd)
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* @resp_len: length of the response buffer
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*
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* Sends a command to the SCM and waits for the command to finish processing.
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*
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* A note on cache maintenance:
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* Note that any buffers that are expected to be accessed by the secure world
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* must be flushed before invoking scm_call and invalidated in the cache
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* immediately after scm_call returns. Cache maintenance on the command and
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* response buffers is taken care of by scm_call; however, callers are
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* responsible for any other cached buffers passed over to the secure world.
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*/
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int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
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void *resp_buf, size_t resp_len)
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@ -227,12 +255,13 @@ int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
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int ret;
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struct scm_command *cmd;
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struct scm_response *rsp;
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unsigned long start, end;
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cmd = alloc_scm_command(cmd_len, resp_len);
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if (!cmd)
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return -ENOMEM;
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cmd->id = (svc_id << 10) | cmd_id;
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cmd->id = cpu_to_le32((svc_id << 10) | cmd_id);
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if (cmd_buf)
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memcpy(scm_get_command_buffer(cmd), cmd_buf, cmd_len);
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@ -243,17 +272,15 @@ int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
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goto out;
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rsp = scm_command_to_response(cmd);
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start = (unsigned long)rsp;
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do {
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u32 start = (u32)rsp;
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u32 end = (u32)scm_get_response_buffer(rsp) + resp_len;
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start &= ~(CACHELINESIZE - 1);
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while (start < end) {
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asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
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: "memory");
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start += CACHELINESIZE;
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}
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scm_inv_range(start, start + sizeof(*rsp));
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} while (!rsp->is_complete);
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end = (unsigned long)scm_get_response_buffer(rsp) + resp_len;
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scm_inv_range(start, end);
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if (resp_buf)
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memcpy(resp_buf, scm_get_response_buffer(rsp), resp_len);
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out:
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