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https://github.com/torvalds/linux
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drivers: net: xgene: Adding support for TSO
Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Iyappan Subramanian
David S. Miller
parent
949c40bb16
commit
9b00eb494d
5 changed files with 262 additions and 24 deletions
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@ -193,12 +193,16 @@ enum xgene_enet_rm {
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#define USERINFO_LEN 32
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#define FPQNUM_POS 32
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#define FPQNUM_LEN 12
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#define NV_POS 50
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#define NV_LEN 1
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#define LL_POS 51
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#define LL_LEN 1
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#define LERR_POS 60
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#define LERR_LEN 3
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#define STASH_POS 52
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#define STASH_LEN 2
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#define BUFDATALEN_POS 48
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#define BUFDATALEN_LEN 12
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#define BUFDATALEN_LEN 15
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#define DATAADDR_POS 0
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#define DATAADDR_LEN 42
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#define COHERENT_POS 63
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@ -215,9 +219,19 @@ enum xgene_enet_rm {
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#define IPHDR_LEN 6
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#define EC_POS 22 /* Enable checksum */
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#define EC_LEN 1
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#define ET_POS 23 /* Enable TSO */
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#define IS_POS 24 /* IP protocol select */
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#define IS_LEN 1
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#define TYPE_ETH_WORK_MESSAGE_POS 44
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#define LL_BYTES_MSB_POS 56
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#define LL_BYTES_MSB_LEN 8
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#define LL_BYTES_LSB_POS 48
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#define LL_BYTES_LSB_LEN 12
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#define LL_LEN_POS 48
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#define LL_LEN_LEN 8
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#define DATALEN_MASK GENMASK(11, 0)
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#define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS)
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struct xgene_enet_raw_desc {
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__le64 m0;
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@ -147,18 +147,27 @@ static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
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{
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struct sk_buff *skb;
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struct device *dev;
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skb_frag_t *frag;
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dma_addr_t *frag_dma_addr;
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u16 skb_index;
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u8 status;
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int ret = 0;
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int i, ret = 0;
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skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
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skb = cp_ring->cp_skb[skb_index];
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frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS];
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dev = ndev_to_dev(cp_ring->ndev);
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dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
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GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1)),
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skb_headlen(skb),
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DMA_TO_DEVICE);
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for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
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frag = &skb_shinfo(skb)->frags[i];
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dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag),
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DMA_TO_DEVICE);
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}
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/* Checking for error */
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status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
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if (unlikely(status > 2)) {
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@ -179,12 +188,16 @@ static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
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static u64 xgene_enet_work_msg(struct sk_buff *skb)
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{
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struct net_device *ndev = skb->dev;
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struct xgene_enet_pdata *pdata = netdev_priv(ndev);
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struct iphdr *iph;
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u8 l3hlen, l4hlen = 0;
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u8 csum_enable = 0;
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u8 proto = 0;
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u8 ethhdr;
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u64 hopinfo;
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u8 l3hlen = 0, l4hlen = 0;
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u8 ethhdr, proto = 0, csum_enable = 0;
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u64 hopinfo = 0;
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u32 hdr_len, mss = 0;
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u32 i, len, nr_frags;
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ethhdr = xgene_enet_hdr_len(skb->data);
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if (unlikely(skb->protocol != htons(ETH_P_IP)) &&
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unlikely(skb->protocol != htons(ETH_P_8021Q)))
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@ -201,14 +214,40 @@ static u64 xgene_enet_work_msg(struct sk_buff *skb)
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l4hlen = tcp_hdrlen(skb) >> 2;
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csum_enable = 1;
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proto = TSO_IPPROTO_TCP;
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if (ndev->features & NETIF_F_TSO) {
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hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb);
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mss = skb_shinfo(skb)->gso_size;
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if (skb_is_nonlinear(skb)) {
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len = skb_headlen(skb);
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nr_frags = skb_shinfo(skb)->nr_frags;
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for (i = 0; i < 2 && i < nr_frags; i++)
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len += skb_shinfo(skb)->frags[i].size;
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/* HW requires header must reside in 3 buffer */
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if (unlikely(hdr_len > len)) {
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if (skb_linearize(skb))
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return 0;
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}
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}
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if (!mss || ((skb->len - hdr_len) <= mss))
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goto out;
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if (mss != pdata->mss) {
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pdata->mss = mss;
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pdata->mac_ops->set_mss(pdata);
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}
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hopinfo |= SET_BIT(ET);
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}
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} else if (iph->protocol == IPPROTO_UDP) {
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l4hlen = UDP_HDR_SIZE;
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csum_enable = 1;
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}
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out:
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l3hlen = ip_hdrlen(skb) >> 2;
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ethhdr = xgene_enet_hdr_len(skb->data);
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hopinfo = SET_VAL(TCPHDR, l4hlen) |
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hopinfo |= SET_VAL(TCPHDR, l4hlen) |
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SET_VAL(IPHDR, l3hlen) |
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SET_VAL(ETHHDR, ethhdr) |
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SET_VAL(EC, csum_enable) |
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@ -224,20 +263,54 @@ static u16 xgene_enet_encode_len(u16 len)
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return (len == BUFLEN_16K) ? 0 : len;
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}
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static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len)
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{
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desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) |
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SET_VAL(BUFDATALEN, len));
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}
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static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring)
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{
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__le64 *exp_bufs;
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exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS];
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memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS);
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ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1);
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return exp_bufs;
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}
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static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring)
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{
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return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS];
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}
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static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
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struct sk_buff *skb)
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{
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struct device *dev = ndev_to_dev(tx_ring->ndev);
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struct xgene_enet_raw_desc *raw_desc;
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dma_addr_t dma_addr;
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__le64 *exp_desc = NULL, *exp_bufs = NULL;
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dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr;
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skb_frag_t *frag;
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u16 tail = tx_ring->tail;
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u64 hopinfo;
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u32 len, hw_len;
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u8 count = 1;
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u8 ll = 0, nv = 0, idx = 0;
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bool split = false;
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u32 size, offset, ell_bytes = 0;
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u32 i, fidx, nr_frags, count = 1;
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raw_desc = &tx_ring->raw_desc[tail];
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tail = (tail + 1) & (tx_ring->slots - 1);
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memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
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hopinfo = xgene_enet_work_msg(skb);
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if (!hopinfo)
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return -EINVAL;
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raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
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hopinfo);
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len = skb_headlen(skb);
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hw_len = xgene_enet_encode_len(len);
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@ -252,13 +325,100 @@ static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
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SET_VAL(BUFDATALEN, hw_len) |
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SET_BIT(COHERENT));
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raw_desc->m0 = cpu_to_le64(SET_VAL(USERINFO, tail));
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hopinfo = xgene_enet_work_msg(skb);
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raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
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hopinfo);
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tx_ring->cp_ring->cp_skb[tail] = skb;
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if (!skb_is_nonlinear(skb))
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goto out;
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/* scatter gather */
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nv = 1;
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exp_desc = (void *)&tx_ring->raw_desc[tail];
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tail = (tail + 1) & (tx_ring->slots - 1);
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memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc));
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nr_frags = skb_shinfo(skb)->nr_frags;
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for (i = nr_frags; i < 4 ; i++)
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exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER);
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frag_dma_addr = xgene_get_frag_dma_array(tx_ring);
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for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) {
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if (!split) {
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frag = &skb_shinfo(skb)->frags[fidx];
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size = skb_frag_size(frag);
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offset = 0;
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pbuf_addr = skb_frag_dma_map(dev, frag, 0, size,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev, pbuf_addr))
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return -EINVAL;
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frag_dma_addr[fidx] = pbuf_addr;
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fidx++;
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if (size > BUFLEN_16K)
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split = true;
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}
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if (size > BUFLEN_16K) {
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len = BUFLEN_16K;
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size -= BUFLEN_16K;
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} else {
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len = size;
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split = false;
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}
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dma_addr = pbuf_addr + offset;
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hw_len = xgene_enet_encode_len(len);
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switch (i) {
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case 0:
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case 1:
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case 2:
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xgene_set_addr_len(exp_desc, i, dma_addr, hw_len);
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break;
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case 3:
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if (split || (fidx != nr_frags)) {
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exp_bufs = xgene_enet_get_exp_bufs(tx_ring);
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xgene_set_addr_len(exp_bufs, idx, dma_addr,
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hw_len);
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idx++;
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ell_bytes += len;
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} else {
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xgene_set_addr_len(exp_desc, i, dma_addr,
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hw_len);
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}
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break;
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default:
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xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len);
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idx++;
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ell_bytes += len;
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break;
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}
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if (split)
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offset += BUFLEN_16K;
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}
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count++;
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if (idx) {
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ll = 1;
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dma_addr = dma_map_single(dev, exp_bufs,
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sizeof(u64) * MAX_EXP_BUFFS,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev, dma_addr)) {
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dev_kfree_skb_any(skb);
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return -EINVAL;
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}
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i = ell_bytes >> LL_BYTES_LSB_LEN;
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exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
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SET_VAL(LL_BYTES_MSB, i) |
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SET_VAL(LL_LEN, idx));
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raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes));
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}
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out:
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raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) |
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SET_VAL(USERINFO, tx_ring->tail));
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tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb;
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tx_ring->tail = tail;
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return count;
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@ -281,6 +441,9 @@ static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
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return NETDEV_TX_BUSY;
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}
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if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE))
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return NETDEV_TX_OK;
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count = xgene_enet_setup_tx_desc(tx_ring, skb);
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if (count <= 0) {
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dev_kfree_skb_any(skb);
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@ -341,7 +504,7 @@ static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring,
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/* strip off CRC as HW isn't doing this */
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datalen = GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1));
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datalen -= 4;
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datalen = (datalen & DATALEN_MASK) - 4;
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prefetch(skb->data - NET_IP_ALIGN);
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skb_put(skb, datalen);
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@ -373,26 +536,41 @@ static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
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int budget)
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{
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struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
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struct xgene_enet_raw_desc *raw_desc;
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struct xgene_enet_raw_desc *raw_desc, *exp_desc;
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u16 head = ring->head;
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u16 slots = ring->slots - 1;
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int ret, count = 0;
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int ret, count = 0, processed = 0;
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do {
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raw_desc = &ring->raw_desc[head];
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exp_desc = NULL;
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if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc)))
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break;
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/* read fpqnum field after dataaddr field */
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dma_rmb();
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if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) {
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head = (head + 1) & slots;
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exp_desc = &ring->raw_desc[head];
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if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) {
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head = (head - 1) & slots;
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break;
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}
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dma_rmb();
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count++;
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}
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if (is_rx_desc(raw_desc))
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ret = xgene_enet_rx_frame(ring, raw_desc);
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else
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ret = xgene_enet_tx_completion(ring, raw_desc);
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xgene_enet_mark_desc_slot_empty(raw_desc);
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if (exp_desc)
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xgene_enet_mark_desc_slot_empty(exp_desc);
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head = (head + 1) & slots;
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count++;
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processed++;
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if (ret)
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break;
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@ -408,7 +586,7 @@ static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
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}
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}
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return count;
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return processed;
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}
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static int xgene_enet_napi(struct napi_struct *napi, const int budget)
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@ -753,12 +931,13 @@ static int xgene_enet_create_desc_rings(struct net_device *ndev)
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struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
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struct xgene_enet_desc_ring *buf_pool = NULL;
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enum xgene_ring_owner owner;
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dma_addr_t dma_exp_bufs;
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u8 cpu_bufnum = pdata->cpu_bufnum;
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u8 eth_bufnum = pdata->eth_bufnum;
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u8 bp_bufnum = pdata->bp_bufnum;
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u16 ring_num = pdata->ring_num;
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u16 ring_id;
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int ret;
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int ret, size;
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/* allocate rx descriptor ring */
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owner = xgene_derive_ring_owner(pdata);
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@ -809,6 +988,15 @@ static int xgene_enet_create_desc_rings(struct net_device *ndev)
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ret = -ENOMEM;
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goto err;
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}
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size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS;
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tx_ring->exp_bufs = dma_zalloc_coherent(dev, size, &dma_exp_bufs,
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GFP_KERNEL);
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if (!tx_ring->exp_bufs) {
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ret = -ENOMEM;
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goto err;
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}
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pdata->tx_ring = tx_ring;
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if (!pdata->cq_cnt) {
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@ -833,6 +1021,16 @@ static int xgene_enet_create_desc_rings(struct net_device *ndev)
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ret = -ENOMEM;
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goto err;
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}
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size = sizeof(dma_addr_t) * MAX_SKB_FRAGS;
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cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots,
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size, GFP_KERNEL);
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if (!cp_ring->frag_dma_addr) {
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devm_kfree(dev, cp_ring->cp_skb);
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ret = -ENOMEM;
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goto err;
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}
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pdata->tx_ring->cp_ring = cp_ring;
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pdata->tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring);
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@ -1188,7 +1386,8 @@ static int xgene_enet_probe(struct platform_device *pdev)
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xgene_enet_set_ethtool_ops(ndev);
|
||||
ndev->features |= NETIF_F_IP_CSUM |
|
||||
NETIF_F_GSO |
|
||||
NETIF_F_GRO;
|
||||
NETIF_F_GRO |
|
||||
NETIF_F_SG;
|
||||
|
||||
of_id = of_match_device(xgene_enet_of_match, &pdev->dev);
|
||||
if (of_id) {
|
||||
|
|
@ -1214,6 +1413,12 @@ static int xgene_enet_probe(struct platform_device *pdev)
|
|||
|
||||
xgene_enet_setup_ops(pdata);
|
||||
|
||||
if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
|
||||
ndev->features |= NETIF_F_TSO;
|
||||
pdata->mss = XGENE_ENET_MSS;
|
||||
}
|
||||
ndev->hw_features = ndev->features;
|
||||
|
||||
ret = register_netdev(ndev);
|
||||
if (ret) {
|
||||
netdev_err(ndev, "Failed to register netdev\n");
|
||||
|
|
|
|||
|
|
@ -43,6 +43,9 @@
|
|||
#define BUFLEN_16K (16 * 1024)
|
||||
#define NUM_PKT_BUF 64
|
||||
#define NUM_BUFPOOL 32
|
||||
#define MAX_EXP_BUFFS 256
|
||||
#define XGENE_ENET_MSS 1448
|
||||
#define XGENE_MIN_ENET_FRAME_SIZE 60
|
||||
|
||||
#define START_CPU_BUFNUM_0 0
|
||||
#define START_ETH_BUFNUM_0 2
|
||||
|
|
@ -80,6 +83,7 @@ struct xgene_enet_desc_ring {
|
|||
u16 num;
|
||||
u16 head;
|
||||
u16 tail;
|
||||
u16 exp_buf_tail;
|
||||
u16 slots;
|
||||
u16 irq;
|
||||
char irq_name[IRQ_ID_SIZE];
|
||||
|
|
@ -94,6 +98,7 @@ struct xgene_enet_desc_ring {
|
|||
u8 nbufpool;
|
||||
struct sk_buff *(*rx_skb);
|
||||
struct sk_buff *(*cp_skb);
|
||||
dma_addr_t *frag_dma_addr;
|
||||
enum xgene_enet_ring_cfgsize cfgsize;
|
||||
struct xgene_enet_desc_ring *cp_ring;
|
||||
struct xgene_enet_desc_ring *buf_pool;
|
||||
|
|
@ -103,6 +108,7 @@ struct xgene_enet_desc_ring {
|
|||
struct xgene_enet_raw_desc *raw_desc;
|
||||
struct xgene_enet_raw_desc16 *raw_desc16;
|
||||
};
|
||||
__le64 *exp_bufs;
|
||||
};
|
||||
|
||||
struct xgene_mac_ops {
|
||||
|
|
@ -113,6 +119,7 @@ struct xgene_mac_ops {
|
|||
void (*tx_disable)(struct xgene_enet_pdata *pdata);
|
||||
void (*rx_disable)(struct xgene_enet_pdata *pdata);
|
||||
void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
|
||||
void (*set_mss)(struct xgene_enet_pdata *pdata);
|
||||
void (*link_state)(struct work_struct *work);
|
||||
};
|
||||
|
||||
|
|
@ -171,6 +178,7 @@ struct xgene_enet_pdata {
|
|||
u8 eth_bufnum;
|
||||
u8 bp_bufnum;
|
||||
u16 ring_num;
|
||||
u32 mss;
|
||||
};
|
||||
|
||||
struct xgene_indirect_ctl {
|
||||
|
|
@ -205,6 +213,9 @@ static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
|
|||
#define GET_VAL(field, src) \
|
||||
xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
|
||||
|
||||
#define GET_BIT(field, src) \
|
||||
xgene_enet_get_field_value(field ## _POS, 1, src)
|
||||
|
||||
static inline struct device *ndev_to_dev(struct net_device *ndev)
|
||||
{
|
||||
return ndev->dev.parent;
|
||||
|
|
|
|||
|
|
@ -184,6 +184,11 @@ static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)
|
|||
xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1);
|
||||
}
|
||||
|
||||
static void xgene_xgmac_set_mss(struct xgene_enet_pdata *pdata)
|
||||
{
|
||||
xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR, pdata->mss);
|
||||
}
|
||||
|
||||
static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata)
|
||||
{
|
||||
u32 data;
|
||||
|
|
@ -204,8 +209,8 @@ static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)
|
|||
data &= ~HSTLENCHK;
|
||||
xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);
|
||||
|
||||
xgene_enet_wr_mac(pdata, HSTMAXFRAME_LENGTH_ADDR, 0x06000600);
|
||||
xgene_xgmac_set_mac_addr(pdata);
|
||||
xgene_xgmac_set_mss(pdata);
|
||||
|
||||
xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);
|
||||
data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
|
||||
|
|
@ -329,6 +334,7 @@ struct xgene_mac_ops xgene_xgmac_ops = {
|
|||
.rx_disable = xgene_xgmac_rx_disable,
|
||||
.tx_disable = xgene_xgmac_tx_disable,
|
||||
.set_mac_addr = xgene_xgmac_set_mac_addr,
|
||||
.set_mss = xgene_xgmac_set_mss,
|
||||
.link_state = xgene_enet_link_state
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -62,7 +62,9 @@
|
|||
#define XCLE_BYPASS_REG0_ADDR 0x0160
|
||||
#define XCLE_BYPASS_REG1_ADDR 0x0164
|
||||
#define XG_CFG_BYPASS_ADDR 0x0204
|
||||
#define XG_CFG_LINK_AGGR_RESUME_0_ADDR 0x0214
|
||||
#define XG_LINK_STATUS_ADDR 0x0228
|
||||
#define XG_TSIF_MSS_REG0_ADDR 0x02a4
|
||||
#define XG_ENET_SPARE_CFG_REG_ADDR 0x040c
|
||||
#define XG_ENET_SPARE_CFG_REG_1_ADDR 0x0410
|
||||
#define XGENET_RX_DV_GATE_REG_0_ADDR 0x0804
|
||||
|
|
|
|||
Loading…
Reference in a new issue