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amd64_edac: Fix DCT base address selector

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The correct check is to verify whether in high range we're below 4GB
and not to extract the DctSelBaseAddr again. See "2.8.5 Routing DRAM
Requests" in the F10h BKDG.

Cc: <stable@kernel.org> # .32.x .33.x .34.x
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Acked-by: Doug Thompson <dougthompson@xmission.com>
This commit is contained in:
Borislav Petkov 2010-03-08 18:29:35 +01:00
parent f4347553b3
commit 9975a5f22a
1 changed files with 1 additions and 1 deletions
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2
drivers/edac/amd64_edac.c
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@ -1435,7 +1435,7 @@ static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel,
u64 chan_off;
if (hi_range_sel) {
if (!(dct_sel_base_addr & 0xFFFFF800) &&
if (!(dct_sel_base_addr & 0xFFFF0000) &&
hole_valid && (sys_addr >= 0x100000000ULL))
chan_off = hole_off << 16;
else