mirror of
https://github.com/torvalds/linux
synced 2024-10-18 17:29:25 +00:00
Merge series "Support for Ingenic JZ47xx SPI controller" from Artur Rojek <contact@artur-rojek.eu>:
Hi, This patchset introduces support for SPI controllers found in the Ingenic JZ47xx family of SoCs. Of particular note, this allows to replace GPIO backed SPI on the MIPS Creator CI20 board. Mark: Checkpatch generates a `need consistent spacing around '*'` error on this patchset, however I believe this is a false positive due to it confusing a pointer with multiplication operator inside a macro. Rob: I refrained from adding SPI pin groups into the bindings, as I felt that would be enforcing a policy (SPI signals can be multiplexed on multiple pin groups on the board, per use case). Instead, I included an example pin configuration into the relevant commit description. Other controllers already present in ci20.dts do specify their pin groups, but I think this is bad practice. Do you have particular guidelines on this? Pavel: Feel free to add your Tested-by, if you still have your CI20 setup around :) I tested this driver with two SPI mode MMC/SD card readers and also with the spi-loopback test driver. Cheers, Artur Artur Rojek (2): SPI: add Ingenic JZ47xx driver. MIPS: JZ4780: CI20: DTS: add SPI controller config Paul Cercueil (1): dt-bindings: spi: Document Ingenic SPI controller bindings .../devicetree/bindings/spi/ingenic,spi.yaml | 72 +++ arch/mips/boot/dts/ingenic/ci20.dts | 9 +- arch/mips/boot/dts/ingenic/jz4780.dtsi | 44 +- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-ingenic.c | 482 ++++++++++++++++++ 6 files changed, 602 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/ingenic,spi.yaml create mode 100644 drivers/spi/spi-ingenic.c -- 2.33.0
This commit is contained in:
Mark Brown
commit
9722162f01
72
Documentation/devicetree/bindings/spi/ingenic,spi.yaml
Normal file
72
Documentation/devicetree/bindings/spi/ingenic,spi.yaml
Normal file
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@ -0,0 +1,72 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/ingenic,spi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Ingenic SoCs SPI controller devicetree bindings
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maintainers:
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- Artur Rojek <contact@artur-rojek.eu>
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- Paul Cercueil <paul@crapouillou.net>
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allOf:
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- $ref: /schemas/spi/spi-controller.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- ingenic,jz4750-spi
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- ingenic,jz4780-spi
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- items:
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- enum:
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- ingenic,jz4760-spi
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- ingenic,jz4770-spi
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- const: ingenic,jz4750-spi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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dmas:
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maxItems: 2
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minItems: 2
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dma-names:
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items:
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- const: rx
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- const: tx
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- dmas
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- dma-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/jz4770-cgu.h>
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spi@10043000 {
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compatible = "ingenic,jz4770-spi", "ingenic,jz4750-spi";
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reg = <0x10043000 0x1c>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <8>;
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clocks = <&cgu JZ4770_CLK_SSI0>;
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dmas = <&dmac1 23 0xffffffff>, <&dmac1 22 0xffffffff>;
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dma-names = "rx", "tx";
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};
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@ -113,9 +113,12 @@ &cgu {
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* Use the 32.768 kHz oscillator as the parent of the RTC for a higher
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* precision.
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*/
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assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;
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assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
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assigned-clock-rates = <48000000>;
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assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
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<&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>;
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assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
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<&cgu JZ4780_CLK_MPLL>,
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<&cgu JZ4780_CLK_SSIPLL>;
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assigned-clock-rates = <48000000>, <0>, <54000000>;
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};
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&tcu {
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|
|
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@ -255,22 +255,23 @@ gpf: gpio@5 {
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};
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};
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spi_gpio {
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compatible = "spi-gpio";
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spi0: spi@10043000 {
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compatible = "ingenic,jz4780-spi";
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reg = <0x10043000 0x1c>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-chipselects = <2>;
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gpio-miso = <&gpe 14 0>;
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gpio-sck = <&gpe 15 0>;
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gpio-mosi = <&gpe 17 0>;
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cs-gpios = <&gpe 16 0>, <&gpe 18 0>;
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interrupt-parent = <&intc>;
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interrupts = <8>;
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spidev@0 {
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compatible = "spidev";
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reg = <0>;
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spi-max-frequency = <1000000>;
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};
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clocks = <&cgu JZ4780_CLK_SSI0>;
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clock-names = "spi";
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dmas = <&dma JZ4780_DMA_SSI0_RX 0xffffffff>,
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<&dma JZ4780_DMA_SSI0_TX 0xffffffff>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart0: serial@10030000 {
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@ -338,6 +339,25 @@ uart4: serial@10034000 {
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status = "disabled";
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};
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spi1: spi@10044000 {
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compatible = "ingenic,jz4780-spi";
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reg = <0x10044000 0x1c>;
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#address-cells = <1>;
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#size-sells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <7>;
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clocks = <&cgu JZ4780_CLK_SSI1>;
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clock-names = "spi";
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dmas = <&dma JZ4780_DMA_SSI1_RX 0xffffffff>,
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<&dma JZ4780_DMA_SSI1_TX 0xffffffff>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c0: i2c@10050000 {
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compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
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#address-cells = <1>;
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|
|
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@ -406,6 +406,15 @@ config SPI_IMX
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help
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This enables support for the Freescale i.MX SPI controllers.
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config SPI_INGENIC
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tristate "Ingenic JZ47xx SoCs SPI controller"
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depends on MACH_INGENIC || COMPILE_TEST
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help
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This enables support for the Ingenic JZ47xx SoCs SPI controller.
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To compile this driver as a module, choose M here: the module
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will be called spi-ingenic.
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config SPI_JCORE
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tristate "J-Core SPI Master"
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depends on OF && (SUPERH || COMPILE_TEST)
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|
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@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_HISI_KUNPENG) += spi-hisi-kunpeng.o
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obj-$(CONFIG_SPI_HISI_SFC_V3XX) += spi-hisi-sfc-v3xx.o
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obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
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obj-$(CONFIG_SPI_IMX) += spi-imx.o
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obj-$(CONFIG_SPI_INGENIC) += spi-ingenic.o
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obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o
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obj-$(CONFIG_SPI_JCORE) += spi-jcore.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
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|
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482
drivers/spi/spi-ingenic.c
Normal file
482
drivers/spi/spi-ingenic.c
Normal file
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@ -0,0 +1,482 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SPI bus driver for the Ingenic JZ47xx SoCs
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* Copyright (c) 2017-2021 Artur Rojek <contact@artur-rojek.eu>
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* Copyright (c) 2017-2021 Paul Cercueil <paul@crapouillou.net>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#define REG_SSIDR 0x0
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#define REG_SSICR0 0x4
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#define REG_SSICR1 0x8
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#define REG_SSISR 0xc
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#define REG_SSIGR 0x18
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#define REG_SSICR0_TENDIAN_LSB BIT(19)
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#define REG_SSICR0_RENDIAN_LSB BIT(17)
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#define REG_SSICR0_SSIE BIT(15)
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#define REG_SSICR0_LOOP BIT(10)
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#define REG_SSICR0_EACLRUN BIT(7)
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#define REG_SSICR0_FSEL BIT(6)
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#define REG_SSICR0_TFLUSH BIT(2)
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#define REG_SSICR0_RFLUSH BIT(1)
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#define REG_SSICR1_FRMHL_MASK (BIT(31) | BIT(30))
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#define REG_SSICR1_FRMHL BIT(30)
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#define REG_SSICR1_LFST BIT(25)
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#define REG_SSICR1_UNFIN BIT(23)
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#define REG_SSICR1_PHA BIT(1)
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#define REG_SSICR1_POL BIT(0)
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#define REG_SSISR_END BIT(7)
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#define REG_SSISR_BUSY BIT(6)
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#define REG_SSISR_TFF BIT(5)
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#define REG_SSISR_RFE BIT(4)
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#define REG_SSISR_RFHF BIT(2)
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#define REG_SSISR_UNDR BIT(1)
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#define REG_SSISR_OVER BIT(0)
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#define SPI_INGENIC_FIFO_SIZE 128u
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struct jz_soc_info {
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u32 bits_per_word_mask;
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struct reg_field flen_field;
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bool has_trendian;
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};
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struct ingenic_spi {
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const struct jz_soc_info *soc_info;
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struct clk *clk;
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struct resource *mem_res;
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struct regmap *map;
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struct regmap_field *flen_field;
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};
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static int spi_ingenic_wait(struct ingenic_spi *priv,
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unsigned long mask,
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bool condition)
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{
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unsigned int val;
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return regmap_read_poll_timeout(priv->map, REG_SSISR, val,
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!!(val & mask) == condition,
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100, 10000);
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}
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static void spi_ingenic_set_cs(struct spi_device *spi, bool disable)
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{
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struct ingenic_spi *priv = spi_controller_get_devdata(spi->controller);
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if (disable) {
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regmap_clear_bits(priv->map, REG_SSICR1, REG_SSICR1_UNFIN);
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regmap_clear_bits(priv->map, REG_SSISR,
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REG_SSISR_UNDR | REG_SSISR_OVER);
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spi_ingenic_wait(priv, REG_SSISR_END, true);
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} else {
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regmap_set_bits(priv->map, REG_SSICR1, REG_SSICR1_UNFIN);
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}
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regmap_set_bits(priv->map, REG_SSICR0,
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REG_SSICR0_RFLUSH | REG_SSICR0_TFLUSH);
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}
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static void spi_ingenic_prepare_transfer(struct ingenic_spi *priv,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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unsigned long clk_hz = clk_get_rate(priv->clk);
|
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u32 cdiv, speed_hz = xfer->speed_hz ?: spi->max_speed_hz,
|
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bits_per_word = xfer->bits_per_word ?: spi->bits_per_word;
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|
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cdiv = clk_hz / (speed_hz * 2);
|
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cdiv = clamp(cdiv, 1u, 0x100u) - 1;
|
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|
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regmap_write(priv->map, REG_SSIGR, cdiv);
|
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|
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regmap_field_write(priv->flen_field, bits_per_word - 2);
|
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}
|
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|
||||
static void spi_ingenic_finalize_transfer(void *controller)
|
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{
|
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spi_finalize_current_transfer(controller);
|
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}
|
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|
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static struct dma_async_tx_descriptor *
|
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spi_ingenic_prepare_dma(struct spi_controller *ctlr, struct dma_chan *chan,
|
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struct sg_table *sg, enum dma_transfer_direction dir,
|
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unsigned int bits)
|
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{
|
||||
struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
|
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struct dma_slave_config cfg = {
|
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.direction = dir,
|
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.src_addr = priv->mem_res->start + REG_SSIDR,
|
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.dst_addr = priv->mem_res->start + REG_SSIDR,
|
||||
};
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
dma_cookie_t cookie;
|
||||
int ret;
|
||||
|
||||
if (bits > 16) {
|
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cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
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cfg.src_maxburst = cfg.dst_maxburst = 4;
|
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} else if (bits > 8) {
|
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cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
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cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
||||
cfg.src_maxburst = cfg.dst_maxburst = 2;
|
||||
} else {
|
||||
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
||||
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
||||
cfg.src_maxburst = cfg.dst_maxburst = 1;
|
||||
}
|
||||
|
||||
ret = dmaengine_slave_config(chan, &cfg);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
desc = dmaengine_prep_slave_sg(chan, sg->sgl, sg->nents, dir,
|
||||
DMA_PREP_INTERRUPT);
|
||||
if (!desc)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
if (dir == DMA_DEV_TO_MEM) {
|
||||
desc->callback = spi_ingenic_finalize_transfer;
|
||||
desc->callback_param = ctlr;
|
||||
}
|
||||
|
||||
cookie = dmaengine_submit(desc);
|
||||
|
||||
ret = dma_submit_error(cookie);
|
||||
if (ret) {
|
||||
dmaengine_desc_free(desc);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return desc;
|
||||
}
|
||||
|
||||
static int spi_ingenic_dma_tx(struct spi_controller *ctlr,
|
||||
struct spi_transfer *xfer, unsigned int bits)
|
||||
{
|
||||
struct dma_async_tx_descriptor *rx_desc, *tx_desc;
|
||||
|
||||
rx_desc = spi_ingenic_prepare_dma(ctlr, ctlr->dma_rx,
|
||||
&xfer->rx_sg, DMA_DEV_TO_MEM, bits);
|
||||
if (IS_ERR(rx_desc))
|
||||
return PTR_ERR(rx_desc);
|
||||
|
||||
tx_desc = spi_ingenic_prepare_dma(ctlr, ctlr->dma_tx,
|
||||
&xfer->tx_sg, DMA_MEM_TO_DEV, bits);
|
||||
if (IS_ERR(tx_desc)) {
|
||||
dmaengine_terminate_async(ctlr->dma_rx);
|
||||
dmaengine_desc_free(rx_desc);
|
||||
return PTR_ERR(tx_desc);
|
||||
}
|
||||
|
||||
dma_async_issue_pending(ctlr->dma_rx);
|
||||
dma_async_issue_pending(ctlr->dma_tx);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#define SPI_INGENIC_TX(x) \
|
||||
static int spi_ingenic_tx##x(struct ingenic_spi *priv, \
|
||||
struct spi_transfer *xfer) \
|
||||
{ \
|
||||
unsigned int count = xfer->len / (x / 8); \
|
||||
unsigned int prefill = min(count, SPI_INGENIC_FIFO_SIZE); \
|
||||
const u##x *tx_buf = xfer->tx_buf; \
|
||||
u##x *rx_buf = xfer->rx_buf; \
|
||||
unsigned int i, val; \
|
||||
int err; \
|
||||
\
|
||||
/* Fill up the TX fifo */ \
|
||||
for (i = 0; i < prefill; i++) { \
|
||||
val = tx_buf ? tx_buf[i] : 0; \
|
||||
\
|
||||
regmap_write(priv->map, REG_SSIDR, val); \
|
||||
} \
|
||||
\
|
||||
for (i = 0; i < count; i++) { \
|
||||
err = spi_ingenic_wait(priv, REG_SSISR_RFE, false); \
|
||||
if (err) \
|
||||
return err; \
|
||||
\
|
||||
regmap_read(priv->map, REG_SSIDR, &val); \
|
||||
if (rx_buf) \
|
||||
rx_buf[i] = val; \
|
||||
\
|
||||
if (i < count - prefill) { \
|
||||
val = tx_buf ? tx_buf[i + prefill] : 0; \
|
||||
\
|
||||
regmap_write(priv->map, REG_SSIDR, val); \
|
||||
} \
|
||||
} \
|
||||
\
|
||||
return 0; \
|
||||
}
|
||||
SPI_INGENIC_TX(8)
|
||||
SPI_INGENIC_TX(16)
|
||||
SPI_INGENIC_TX(32)
|
||||
#undef SPI_INGENIC_TX
|
||||
|
||||
static int spi_ingenic_transfer_one(struct spi_controller *ctlr,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
|
||||
unsigned int bits = xfer->bits_per_word ?: spi->bits_per_word;
|
||||
bool can_dma = ctlr->can_dma && ctlr->can_dma(ctlr, spi, xfer);
|
||||
|
||||
spi_ingenic_prepare_transfer(priv, spi, xfer);
|
||||
|
||||
if (ctlr->cur_msg_mapped && can_dma)
|
||||
return spi_ingenic_dma_tx(ctlr, xfer, bits);
|
||||
|
||||
if (bits > 16)
|
||||
return spi_ingenic_tx32(priv, xfer);
|
||||
|
||||
if (bits > 8)
|
||||
return spi_ingenic_tx16(priv, xfer);
|
||||
|
||||
return spi_ingenic_tx8(priv, xfer);
|
||||
}
|
||||
|
||||
static int spi_ingenic_prepare_message(struct spi_controller *ctlr,
|
||||
struct spi_message *message)
|
||||
{
|
||||
struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
|
||||
struct spi_device *spi = message->spi;
|
||||
unsigned int cs = REG_SSICR1_FRMHL << spi->chip_select;
|
||||
unsigned int ssicr0_mask = REG_SSICR0_LOOP | REG_SSICR0_FSEL;
|
||||
unsigned int ssicr1_mask = REG_SSICR1_PHA | REG_SSICR1_POL | cs;
|
||||
unsigned int ssicr0 = 0, ssicr1 = 0;
|
||||
|
||||
if (priv->soc_info->has_trendian) {
|
||||
ssicr0_mask |= REG_SSICR0_RENDIAN_LSB | REG_SSICR0_TENDIAN_LSB;
|
||||
|
||||
if (spi->mode & SPI_LSB_FIRST)
|
||||
ssicr0 |= REG_SSICR0_RENDIAN_LSB | REG_SSICR0_TENDIAN_LSB;
|
||||
} else {
|
||||
ssicr1_mask |= REG_SSICR1_LFST;
|
||||
|
||||
if (spi->mode & SPI_LSB_FIRST)
|
||||
ssicr1 |= REG_SSICR1_LFST;
|
||||
}
|
||||
|
||||
if (spi->mode & SPI_LOOP)
|
||||
ssicr0 |= REG_SSICR0_LOOP;
|
||||
if (spi->chip_select)
|
||||
ssicr0 |= REG_SSICR0_FSEL;
|
||||
|
||||
if (spi->mode & SPI_CPHA)
|
||||
ssicr1 |= REG_SSICR1_PHA;
|
||||
if (spi->mode & SPI_CPOL)
|
||||
ssicr1 |= REG_SSICR1_POL;
|
||||
if (spi->mode & SPI_CS_HIGH)
|
||||
ssicr1 |= cs;
|
||||
|
||||
regmap_update_bits(priv->map, REG_SSICR0, ssicr0_mask, ssicr0);
|
||||
regmap_update_bits(priv->map, REG_SSICR1, ssicr1_mask, ssicr1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_ingenic_prepare_hardware(struct spi_controller *ctlr)
|
||||
{
|
||||
struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap_write(priv->map, REG_SSICR0, REG_SSICR0_EACLRUN);
|
||||
regmap_write(priv->map, REG_SSICR1, 0);
|
||||
regmap_write(priv->map, REG_SSISR, 0);
|
||||
regmap_set_bits(priv->map, REG_SSICR0, REG_SSICR0_SSIE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_ingenic_unprepare_hardware(struct spi_controller *ctlr)
|
||||
{
|
||||
struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
|
||||
|
||||
regmap_clear_bits(priv->map, REG_SSICR0, REG_SSICR0_SSIE);
|
||||
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool spi_ingenic_can_dma(struct spi_controller *ctlr,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
struct dma_slave_caps caps;
|
||||
int ret;
|
||||
|
||||
ret = dma_get_slave_caps(ctlr->dma_tx, &caps);
|
||||
if (ret) {
|
||||
dev_err(&spi->dev, "Unable to get slave caps: %d\n", ret);
|
||||
return false;
|
||||
}
|
||||
|
||||
return !caps.max_sg_burst ||
|
||||
xfer->len <= caps.max_sg_burst * SPI_INGENIC_FIFO_SIZE;
|
||||
}
|
||||
|
||||
static int spi_ingenic_request_dma(struct spi_controller *ctlr,
|
||||
struct device *dev)
|
||||
{
|
||||
ctlr->dma_tx = dma_request_slave_channel(dev, "tx");
|
||||
if (!ctlr->dma_tx)
|
||||
return -ENODEV;
|
||||
|
||||
ctlr->dma_rx = dma_request_slave_channel(dev, "rx");
|
||||
|
||||
if (!ctlr->dma_rx)
|
||||
return -ENODEV;
|
||||
|
||||
ctlr->can_dma = spi_ingenic_can_dma;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void spi_ingenic_release_dma(void *data)
|
||||
{
|
||||
struct spi_controller *ctlr = data;
|
||||
|
||||
if (ctlr->dma_tx)
|
||||
dma_release_channel(ctlr->dma_tx);
|
||||
if (ctlr->dma_rx)
|
||||
dma_release_channel(ctlr->dma_rx);
|
||||
}
|
||||
|
||||
static const struct regmap_config spi_ingenic_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = REG_SSIGR,
|
||||
};
|
||||
|
||||
static int spi_ingenic_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct jz_soc_info *pdata;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct spi_controller *ctlr;
|
||||
struct ingenic_spi *priv;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
pdata = of_device_get_match_data(dev);
|
||||
if (!pdata) {
|
||||
dev_err(dev, "Missing platform data.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ctlr = devm_spi_alloc_master(dev, sizeof(*priv));
|
||||
if (!ctlr) {
|
||||
dev_err(dev, "Unable to allocate SPI controller.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
priv = spi_controller_get_devdata(ctlr);
|
||||
priv->soc_info = pdata;
|
||||
|
||||
priv->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(priv->clk)) {
|
||||
return dev_err_probe(dev, PTR_ERR(priv->clk),
|
||||
"Unable to get clock.\n");
|
||||
}
|
||||
|
||||
base = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->mem_res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
priv->map = devm_regmap_init_mmio(dev, base, &spi_ingenic_regmap_config);
|
||||
if (IS_ERR(priv->map))
|
||||
return PTR_ERR(priv->map);
|
||||
|
||||
priv->flen_field = devm_regmap_field_alloc(dev, priv->map,
|
||||
pdata->flen_field);
|
||||
if (IS_ERR(priv->flen_field))
|
||||
return PTR_ERR(priv->flen_field);
|
||||
|
||||
platform_set_drvdata(pdev, ctlr);
|
||||
|
||||
ctlr->prepare_transfer_hardware = spi_ingenic_prepare_hardware;
|
||||
ctlr->unprepare_transfer_hardware = spi_ingenic_unprepare_hardware;
|
||||
ctlr->prepare_message = spi_ingenic_prepare_message;
|
||||
ctlr->set_cs = spi_ingenic_set_cs;
|
||||
ctlr->transfer_one = spi_ingenic_transfer_one;
|
||||
ctlr->mode_bits = SPI_MODE_3 | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH;
|
||||
ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
|
||||
ctlr->max_dma_len = SPI_INGENIC_FIFO_SIZE;
|
||||
ctlr->bits_per_word_mask = pdata->bits_per_word_mask;
|
||||
ctlr->min_speed_hz = 7200;
|
||||
ctlr->max_speed_hz = 54000000;
|
||||
ctlr->num_chipselect = 2;
|
||||
ctlr->dev.of_node = pdev->dev.of_node;
|
||||
|
||||
if (spi_ingenic_request_dma(ctlr, dev))
|
||||
dev_warn(dev, "DMA not available.\n");
|
||||
|
||||
ret = devm_add_action_or_reset(dev, spi_ingenic_release_dma, ctlr);
|
||||
if (ret) {
|
||||
dev_err(dev, "Unable to add action.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_spi_register_controller(dev, ctlr);
|
||||
if (ret)
|
||||
dev_err(dev, "Unable to register SPI controller.\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct jz_soc_info jz4750_soc_info = {
|
||||
.bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 17),
|
||||
.flen_field = REG_FIELD(REG_SSICR1, 4, 7),
|
||||
.has_trendian = false,
|
||||
};
|
||||
|
||||
static const struct jz_soc_info jz4780_soc_info = {
|
||||
.bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
|
||||
.flen_field = REG_FIELD(REG_SSICR1, 3, 7),
|
||||
.has_trendian = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id spi_ingenic_of_match[] = {
|
||||
{ .compatible = "ingenic,jz4750-spi", .data = &jz4750_soc_info },
|
||||
{ .compatible = "ingenic,jz4780-spi", .data = &jz4780_soc_info },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, spi_ingenic_of_match);
|
||||
|
||||
static struct platform_driver spi_ingenic_driver = {
|
||||
.driver = {
|
||||
.name = "spi-ingenic",
|
||||
.of_match_table = spi_ingenic_of_match,
|
||||
},
|
||||
.probe = spi_ingenic_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(spi_ingenic_driver);
|
||||
MODULE_DESCRIPTION("SPI bus driver for the Ingenic JZ47xx SoCs");
|
||||
MODULE_AUTHOR("Artur Rojek <contact@artur-rojek.eu>");
|
||||
MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in a new issue