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perf vendor events intel: Update sierraforst events to v1.01

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Update sierraforest events to v1.01 released in:
582bca24aa

Adds the majority of core and uncore events.

Event json automatically generated by:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py

Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240214011820.644458-11-irogers@google.com
This commit is contained in:
Ian Rogers 2024-02-13 17:17:59 -08:00 committed by Namhyung Kim
parent 8972c03353
commit 9626368d42
14 changed files with 6942 additions and 4 deletions
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2
tools/perf/pmu-events/arch/x86/mapfile.csv
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@ -27,7 +27,7 @@ GenuineIntel-6-2E,v4,nehalemex,core
GenuineIntel-6-A7,v1.02,rocketlake,core
GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-8F,v1.17,sapphirerapids,core
GenuineIntel-6-AF,v1.00,sierraforest,core
GenuineIntel-6-AF,v1.01,sierraforest,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v57,skylake,core
GenuineIntel-6-55-[01234],v1.32,skylakex,core

1 Family-model Version Filename EventType
27 GenuineIntel-6-A7 v1.02 rocketlake core
28 GenuineIntel-6-2A v19 sandybridge core
29 GenuineIntel-6-8F v1.17 sapphirerapids core
30 GenuineIntel-6-AF v1.00 v1.01 sierraforest core
31 GenuineIntel-6-(37|4A|4C|4D|5A) v15 silvermont core
32 GenuineIntel-6-(4E|5E|8E|9E|A5|A6) v57 skylake core
33 GenuineIntel-6-55-[01234] v1.32 skylakex core

185
tools/perf/pmu-events/arch/x86/sierraforest/cache.json
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@ -15,6 +15,148 @@
"SampleAfterValue": "200003",
"UMask": "0x4f"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.",
"EventCode": "0x35",
"EventName": "MEM_BOUND_STALLS_IFETCH.ALL",
"SampleAfterValue": "1000003",
"UMask": "0x7f"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
"EventCode": "0x35",
"EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT",
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which hit in the LLC.",
"EventCode": "0x35",
"EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT",
"SampleAfterValue": "1000003",
"UMask": "0x6"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches.",
"EventCode": "0x35",
"EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS",
"SampleAfterValue": "1000003",
"UMask": "0x78"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS_LOAD.ALL",
"SampleAfterValue": "1000003",
"UMask": "0x7f"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT",
"PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC.",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT",
"SampleAfterValue": "1000003",
"UMask": "0x6"
},
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches.",
"EventCode": "0x34",
"EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS",
"SampleAfterValue": "1000003",
"UMask": "0x78"
},
{
"BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache.",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of load ops retired that miss in the L2 cache.",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x1c"
},
{
"BriefDescription": "Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.ALL",
"SampleAfterValue": "20003",
"UMask": "0x7"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
"SampleAfterValue": "20003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.RSV",
"SampleAfterValue": "20003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",
"EventCode": "0x04",
"EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
"SampleAfterValue": "20003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of load ops retired.",
"Data_LA": "1",
@ -143,6 +285,42 @@
"SampleAfterValue": "1000003",
"UMask": "0x5"
},
{
"BriefDescription": "Counts the number of load uops retired that performed one or more locks",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x21"
},
{
"BriefDescription": "Counts the number of memory uops retired that were splits.",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x43"
},
{
"BriefDescription": "Counts the number of retired split load uops.",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"BriefDescription": "Counts the number of retired split store uops.",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x42"
},
{
"BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
"Data_LA": "1",
@ -151,5 +329,12 @@
"PEBS": "2",
"SampleAfterValue": "1000003",
"UMask": "0x6"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ICACHE",
"SampleAfterValue": "1000003",
"UMask": "0x20"
}
]

68
tools/perf/pmu-events/arch/x86/sierraforest/floating-point.json Normal file
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@ -0,0 +1,68 @@
[
{
"BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.",
"CounterMask": "1",
"EventCode": "0xcd",
"EventName": "ARITH.FPDIV_ACTIVE",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting",
"EventCode": "0xc8",
"EventName": "FP_FLOPS_RETIRED.ALL",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x3"
},
{
"BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]",
"Deprecated": "1",
"EventCode": "0xc8",
"EventName": "FP_FLOPS_RETIRED.DP",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]",
"EventCode": "0xc8",
"EventName": "FP_FLOPS_RETIRED.FP32",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]",
"EventCode": "0xc8",
"EventName": "FP_FLOPS_RETIRED.FP64",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]",
"Deprecated": "1",
"EventCode": "0xc8",
"EventName": "FP_FLOPS_RETIRED.SP",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
"SampleAfterValue": "20003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x8"
}
]

16
tools/perf/pmu-events/arch/x86/sierraforest/frontend.json
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@ -1,4 +1,20 @@
[
{
"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
"EventCode": "0x80",

66
tools/perf/pmu-events/arch/x86/sierraforest/memory.json
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@ -1,4 +1,70 @@
[
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
"EventCode": "0x05",
"EventName": "LD_HEAD.ANY_AT_RET",
"SampleAfterValue": "1000003",
"UMask": "0xff"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
"EventCode": "0x05",
"EventName": "LD_HEAD.L1_BOUND_AT_RET",
"SampleAfterValue": "1000003",
"UMask": "0xf4"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
"EventCode": "0x05",
"EventName": "LD_HEAD.L1_MISS_AT_RET",
"SampleAfterValue": "1000003",
"UMask": "0x81"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
"EventCode": "0x05",
"EventName": "LD_HEAD.OTHER_AT_RET",
"PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",
"SampleAfterValue": "1000003",
"UMask": "0xc0"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
"EventCode": "0x05",
"EventName": "LD_HEAD.PGWALK_AT_RET",
"SampleAfterValue": "1000003",
"UMask": "0xa0"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
"EventCode": "0x05",
"EventName": "LD_HEAD.ST_ADDR_AT_RET",
"SampleAfterValue": "1000003",
"UMask": "0x84"
},
{
"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "20003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts misaligned loads that are 4K page splits.",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts misaligned stores that are 4K page splits.",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"EventCode": "0xB7",

16
tools/perf/pmu-events/arch/x86/sierraforest/other.json
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@ -1,4 +1,13 @@
[
{
"BriefDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]",
"Deprecated": "1",
"EventCode": "0xe4",
"EventName": "LBR_INSERTS.ANY",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"EventCode": "0xB7",
@ -16,5 +25,12 @@
"MSRValue": "0x10002",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.",
"EventCode": "0x75",
"EventName": "SERIALIZATION.C01_MS_SCB",
"SampleAfterValue": "200003",
"UMask": "0x4"
}
]

360
tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json
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@ -1,4 +1,12 @@
[
{
"BriefDescription": "Counts the number of cycles when any of the dividers are active.",
"CounterMask": "1",
"EventCode": "0xcd",
"EventName": "ARITH.DIV_ACTIVE",
"SampleAfterValue": "1000003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
"EventCode": "0xc4",
@ -7,6 +15,71 @@
"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
{
"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
{
"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xbf"
},
{
"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
{
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT_CALL",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL",
"Deprecated": "1",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "Counts the number of near CALL branch instructions retired.",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xf9"
},
{
"BriefDescription": "Counts the number of near RET branch instructions retired.",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
{
"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
"EventCode": "0xc5",
@ -15,6 +88,54 @@
"PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
{
"BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
{
"BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
{
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "Counts the number of mispredicted near taken branch instructions retired.",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "1",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
"EventName": "CPU_CLK_UNHALTED.CORE",
@ -67,6 +188,66 @@
"PEBS": "1",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ADDRESS_ALIAS",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
"SampleAfterValue": "20003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.PAGE_FAULT",
"SampleAfterValue": "20003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SLOW",
"SampleAfterValue": "20003",
"UMask": "0x6f"
},
{
"BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of Last Branch Record (LBR) entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY]",
"EventCode": "0xe4",
"EventName": "MISC_RETIRED.LBR_INSERTS",
"PEBS": "1",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
"EventCode": "0x73",
@ -74,23 +255,202 @@
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
"SampleAfterValue": "1000003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.NUKE",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALL",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REGISTER",
"SampleAfterValue": "1000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ALL",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ms",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.CISC",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.DECODE",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH",
"SampleAfterValue": "1000003",
"UMask": "0x8d"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY",
"SampleAfterValue": "1000003",
"UMask": "0x72"
},
{
"BriefDescription": "This event is deprecated. [This event is alias to TOPDOWN_FE_BOUND.ITLB_MISS]",
"Deprecated": "1",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ITLB",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss [This event is alias to TOPDOWN_FE_BOUND.ITLB]",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ITLB_MISS",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.OTHER",
"SampleAfterValue": "1000003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.PREDECODE",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL",
"EventCode": "0x72",
"EventName": "TOPDOWN_RETIRING.ALL",
"PEBS": "1",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of uops issued by the front end every cycle.",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the total number of uops retired.",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of integer divide uops retired.",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.IDIV",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MS",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of x87 uops retired, includes those in ms flows",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.X87",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x2"
}
]

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@ -0,0 +1,10 @@
[
{
"BriefDescription": "B2CXL Clockticks",
"EventCode": "0x01",
"EventName": "UNC_B2CXL_CLOCKTICKS",
"PerPkg": "1",
"PortMask": "0x000",
"Unit": "B2CXL"
}
]

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[
{
"BriefDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"EventCode": "0x02",
"EventName": "UNC_M_ACT_COUNT.ALL",
"PerPkg": "1",
"UMask": "0xf7",
"Unit": "IMC"
},
{
"BriefDescription": "DRAM Activate Count : Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"EventCode": "0x02",
"EventName": "UNC_M_ACT_COUNT.RD",
"PerPkg": "1",
"UMask": "0xf1",
"Unit": "IMC"
},
{
"BriefDescription": "DRAM Activate Count : Underfill Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"EventCode": "0x02",
"EventName": "UNC_M_ACT_COUNT.UFILL",
"PerPkg": "1",
"UMask": "0xf4",
"Unit": "IMC"
},
{
"BriefDescription": "DRAM Activate Count : Write transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"EventCode": "0x02",
"EventName": "UNC_M_ACT_COUNT.WR",
"PerPkg": "1",
"UMask": "0xf2",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 0, all CAS operations",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT_SCH0.ALL",
"PerPkg": "1",
"UMask": "0xff",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 0, all reads",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT_SCH0.RD",
"PerPkg": "1",
"UMask": "0xcf",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 0 regular reads",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT_SCH0.RD_REG",
"PerPkg": "1",
"UMask": "0xc1",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 0 underfill reads",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL",
"PerPkg": "1",
"UMask": "0xc4",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 0, all writes",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT_SCH0.WR",
"PerPkg": "1",
"UMask": "0xf0",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 0 regular writes",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT_SCH0.WR_NONPRE",
"PerPkg": "1",
"UMask": "0xd0",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 0 auto-precharge writes",
"EventCode": "0x05",
"EventName": "UNC_M_CAS_COUNT_SCH0.WR_PRE",
"PerPkg": "1",
"UMask": "0xe0",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 1, all CAS operations",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_COUNT_SCH1.ALL",
"PerPkg": "1",
"UMask": "0xff",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 1, all reads",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_COUNT_SCH1.RD",
"PerPkg": "1",
"UMask": "0xcf",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 1 regular reads",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_COUNT_SCH1.RD_REG",
"PerPkg": "1",
"UMask": "0xc1",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 1 underfill reads",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL",
"PerPkg": "1",
"UMask": "0xc4",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 1, all writes",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_COUNT_SCH1.WR",
"PerPkg": "1",
"UMask": "0xf0",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 1 regular writes",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_COUNT_SCH1.WR_NONPRE",
"PerPkg": "1",
"UMask": "0xd0",
"Unit": "IMC"
},
{
"BriefDescription": "CAS count for SubChannel 1 auto-precharge writes",
"EventCode": "0x06",
"EventName": "UNC_M_CAS_COUNT_SCH1.WR_PRE",
"PerPkg": "1",
"UMask": "0xe0",
"Unit": "IMC"
},
{
"BriefDescription": "Number of DRAM DCLK clock cycles while the event is enabled",
"EventCode": "0x01",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "DRAM Clockticks",
"UMask": "0x1",
"Unit": "IMC"
},
{
"BriefDescription": "Number of DRAM HCLK clock cycles while the event is enabled",
"EventCode": "0x01",
"EventName": "UNC_M_HCLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "DRAM Clockticks",
"Unit": "IMC"
},
{
"BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.ALL",
"PerPkg": "1",
"UMask": "0xff",
"Unit": "IMC"
},
{
"BriefDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.PGT",
"PerPkg": "1",
"UMask": "0xf8",
"Unit": "IMC"
},
{
"BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
"UMask": "0xf1",
"Unit": "IMC"
},
{
"BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.UFILL",
"PerPkg": "1",
"UMask": "0xf4",
"Unit": "IMC"
},
{
"BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
"UMask": "0xf2",
"Unit": "IMC"
},
{
"BriefDescription": "Read buffer inserts on subchannel 0",
"EventCode": "0x17",
"EventName": "UNC_M_RDB_INSERTS.SCH0",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IMC"
},
{
"BriefDescription": "Read buffer inserts on subchannel 1",
"EventCode": "0x17",
"EventName": "UNC_M_RDB_INSERTS.SCH1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IMC"
},
{
"BriefDescription": "Read buffer occupancy on subchannel 0",
"EventCode": "0x1a",
"EventName": "UNC_M_RDB_OCCUPANCY_SCH0",
"PerPkg": "1",
"Unit": "IMC"
},
{
"BriefDescription": "Read buffer occupancy on subchannel 1",
"EventCode": "0x1b",
"EventName": "UNC_M_RDB_OCCUPANCY_SCH1",
"PerPkg": "1",
"Unit": "IMC"
},
{
"BriefDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS.PCH0",
"PerPkg": "1",
"UMask": "0x50",
"Unit": "IMC"
},
{
"BriefDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS.PCH1",
"PerPkg": "1",
"UMask": "0xa0",
"Unit": "IMC"
},
{
"BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 0",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH0",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IMC"
},
{
"BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 1",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IMC"
},
{
"BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 0",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH0",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IMC"
},
{
"BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 1",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IMC"
},
{
"BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 0",
"EventCode": "0x80",
"EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH0",
"PerPkg": "1",
"Unit": "IMC"
},
{
"BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 1",
"EventCode": "0x81",
"EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH1",
"PerPkg": "1",
"Unit": "IMC"
},
{
"BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 0",
"EventCode": "0x82",
"EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH0",
"PerPkg": "1",
"Unit": "IMC"
},
{
"BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 1",
"EventCode": "0x83",
"EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH1",
"PerPkg": "1",
"Unit": "IMC"
},
{
"BriefDescription": "Write Pending Queue Allocations",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_INSERTS.PCH0",
"PerPkg": "1",
"UMask": "0x50",
"Unit": "IMC"
},
{
"BriefDescription": "Write Pending Queue Allocations",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_INSERTS.PCH1",
"PerPkg": "1",
"UMask": "0xa0",
"Unit": "IMC"
},
{
"BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 0",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH0",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IMC"
},
{
"BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 1",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IMC"
},
{
"BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 0",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH0",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IMC"
},
{
"BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 1",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IMC"
},
{
"BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 0",
"EventCode": "0x84",
"EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH0",
"PerPkg": "1",
"Unit": "IMC"
},
{
"BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 1",
"EventCode": "0x85",
"EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH1",
"PerPkg": "1",
"Unit": "IMC"
},
{
"BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 0",
"EventCode": "0x86",
"EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH0",
"PerPkg": "1",
"Unit": "IMC"
},
{
"BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 1",
"EventCode": "0x87",
"EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH1",
"PerPkg": "1",
"Unit": "IMC"
}
]

10
tools/perf/pmu-events/arch/x86/sierraforest/uncore-power.json Normal file
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@ -0,0 +1,10 @@
[
{
"BriefDescription": "PCU Clockticks",
"EventCode": "0x01",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "PCU Clockticks: The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU"
}
]

113
tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json
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@ -1,18 +1,94 @@
[
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.",
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses.",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "1000003",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB.",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "1000003",
"SampleAfterValue": "2000003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSED_WALK",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
"EventCode": "0x85",
@ -20,5 +96,36 @@
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding for iside in PMH every cycle.",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
"EventCode": "0x05",
"EventName": "LD_HEAD.DTLB_MISS_AT_RET",
"SampleAfterValue": "1000003",
"UMask": "0x90"
}
]