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mmc: sdhci-esdhc-imx: add basic imx6q usdhc support
This patch adds the basic support for imx6q usdhc, which is a derivative of esdhc controller. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
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@ -130,13 +130,13 @@ config MMC_SDHCI_CNS3XXX
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If unsure, say N.
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config MMC_SDHCI_ESDHC_IMX
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tristate "SDHCI platform support for the Freescale eSDHC i.MX controller"
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tristate "SDHCI support for the Freescale eSDHC/uSDHC i.MX controller"
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depends on ARCH_MXC
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depends on MMC_SDHCI_PLTFM
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select MMC_SDHCI_IO_ACCESSORS
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help
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This selects the Freescale eSDHC controller support on the platform
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bus, found on i.MX25, i.MX35 and i.MX5x.
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This selects the Freescale eSDHC/uSDHC controller support
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found on i.MX25, i.MX35 i.MX5x and i.MX6x.
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If you have a controller with this interface, say Y or M here.
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@ -32,6 +32,7 @@
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/* VENDOR SPEC register */
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#define SDHCI_VENDOR_SPEC 0xC0
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#define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002
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#define SDHCI_MIX_CTRL 0x48
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/*
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* There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
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@ -59,6 +60,7 @@ enum imx_esdhc_type {
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IMX35_ESDHC,
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IMX51_ESDHC,
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IMX53_ESDHC,
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IMX6Q_USDHC,
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};
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struct pltfm_imx_data {
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@ -81,6 +83,9 @@ static struct platform_device_id imx_esdhc_devtype[] = {
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}, {
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.name = "sdhci-esdhc-imx53",
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.driver_data = IMX53_ESDHC,
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}, {
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.name = "sdhci-usdhc-imx6q",
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.driver_data = IMX6Q_USDHC,
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}, {
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/* sentinel */
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}
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@ -92,6 +97,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
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{ .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
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{ .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
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{ .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
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{ .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
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@ -116,6 +122,11 @@ static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
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return data->devtype == IMX53_ESDHC;
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}
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static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
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{
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return data->devtype == IMX6Q_USDHC;
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}
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static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
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{
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void __iomem *base = host->ioaddr + (reg & ~0x3);
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@ -220,8 +231,16 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
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static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
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{
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if (unlikely(reg == SDHCI_HOST_VERSION))
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reg ^= 2;
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if (unlikely(reg == SDHCI_HOST_VERSION)) {
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u16 val = readw(host->ioaddr + (reg ^ 2));
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/*
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* uSDHC supports SDHCI v3.0, but it's encoded as value
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* 0x3 in host controller version register, which violates
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* SDHCI_SPEC_300 definition. Work it around here.
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*/
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if ((val & SDHCI_SPEC_VER_MASK) == 3)
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return --val;
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}
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return readw(host->ioaddr + reg);
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}
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@ -252,8 +271,17 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
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if ((host->cmd->opcode == MMC_STOP_TRANSMISSION)
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&& (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
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val |= SDHCI_CMD_ABORTCMD;
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writel(val << 16 | imx_data->scratchpad,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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if (is_imx6q_usdhc(imx_data)) {
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u32 m = readl(host->ioaddr + SDHCI_MIX_CTRL);
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m = imx_data->scratchpad | (m & 0xffff0000);
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writel(m, host->ioaddr + SDHCI_MIX_CTRL);
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writel(val << 16,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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} else {
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writel(val << 16 | imx_data->scratchpad,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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}
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return;
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case SDHCI_BLOCK_SIZE:
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val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
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