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drm/xe/hwmon: Expose card reactive critical power
Expose the card reactive critical (I1) power. I1 is exposed as power1_crit in microwatts (typically for client products) or as curr1_crit in milliamperes (typically for server). v2: Move PCODE_MBOX macro to pcode file (Riana) v3: s/IS_DG2/(gt_to_xe(gt)->info.platform == XE_DG2) v4: Fix review comments (Andi) Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/20230925081842.3566834-3-badal.nilawar@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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@ -20,3 +20,29 @@ Description: RO. Card default power limit (default TDP setting).
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Only supported for particular Intel xe graphics platforms.
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What: /sys/devices/.../hwmon/hwmon<i>/power1_crit
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Date: September 2023
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KernelVersion: 6.5
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Contact: intel-xe@lists.freedesktop.org
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Description: RW. Card reactive critical (I1) power limit in microwatts.
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Card reactive critical (I1) power limit in microwatts is exposed
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for client products. The power controller will throttle the
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operating frequency if the power averaged over a window exceeds
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this limit.
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Only supported for particular Intel xe graphics platforms.
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What: /sys/devices/.../hwmon/hwmon<i>/curr1_crit
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Date: September 2023
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KernelVersion: 6.5
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Contact: intel-xe@lists.freedesktop.org
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Description: RW. Card reactive critical (I1) power limit in milliamperes.
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Card reactive critical (I1) power limit in milliamperes is
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exposed for server products. The power controller will throttle
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the operating frequency if the power averaged over a window
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exceeds this limit.
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Only supported for particular Intel xe graphics platforms.
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@ -12,6 +12,8 @@
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#include "xe_gt.h"
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#include "xe_hwmon.h"
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#include "xe_mmio.h"
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#include "xe_pcode.h"
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#include "xe_pcode_api.h"
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enum xe_hwmon_reg {
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REG_PKG_RAPL_LIMIT,
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@ -29,6 +31,7 @@ enum xe_hwmon_reg_operation {
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* SF_* - scale factors for particular quantities according to hwmon spec.
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*/
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#define SF_POWER 1000000 /* microwatts */
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#define SF_CURR 1000 /* milliamperes */
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struct xe_hwmon {
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struct device *hwmon_dev;
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@ -184,18 +187,43 @@ static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
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}
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static const struct hwmon_channel_info *hwmon_info[] = {
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HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
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HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
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HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
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NULL
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};
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/* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
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static int xe_hwmon_pcode_read_i1(struct xe_gt *gt, u32 *uval)
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{
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/* Avoid Illegal Subcommand error */
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if (gt_to_xe(gt)->info.platform == XE_DG2)
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return -ENXIO;
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return xe_pcode_read(gt, PCODE_MBOX(PCODE_POWER_SETUP,
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POWER_SETUP_SUBCOMMAND_READ_I1, 0),
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uval, 0);
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}
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static int xe_hwmon_pcode_write_i1(struct xe_gt *gt, u32 uval)
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{
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return xe_pcode_write(gt, PCODE_MBOX(PCODE_POWER_SETUP,
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POWER_SETUP_SUBCOMMAND_WRITE_I1, 0),
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uval);
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}
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static umode_t
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xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
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{
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u32 uval;
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switch (attr) {
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case hwmon_power_max:
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return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
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case hwmon_power_rated_max:
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return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
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case hwmon_power_crit:
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return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) ||
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!(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
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default:
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return 0;
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}
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@ -204,11 +232,23 @@ xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
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static int
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xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
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{
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int ret;
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u32 uval;
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switch (attr) {
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case hwmon_power_max:
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return xe_hwmon_power_max_read(hwmon, val);
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case hwmon_power_rated_max:
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return xe_hwmon_power_rated_max_read(hwmon, val);
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case hwmon_power_crit:
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ret = xe_hwmon_pcode_read_i1(hwmon->gt, &uval);
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if (ret)
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return ret;
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if (!(uval & POWER_SETUP_I1_WATTS))
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return -ENODEV;
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*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
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SF_POWER, POWER_SETUP_I1_SHIFT);
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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@ -217,9 +257,63 @@ xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
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static int
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xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
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{
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u32 uval;
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switch (attr) {
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case hwmon_power_max:
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return xe_hwmon_power_max_write(hwmon, val);
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case hwmon_power_crit:
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uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER);
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return xe_hwmon_pcode_write_i1(hwmon->gt, uval);
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default:
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return -EOPNOTSUPP;
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}
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}
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static umode_t
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xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr)
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{
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u32 uval;
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switch (attr) {
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case hwmon_curr_crit:
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return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) ||
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(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
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default:
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return 0;
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}
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}
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static int
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xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, long *val)
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{
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int ret;
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u32 uval;
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switch (attr) {
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case hwmon_curr_crit:
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ret = xe_hwmon_pcode_read_i1(hwmon->gt, &uval);
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if (ret)
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return ret;
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if (uval & POWER_SETUP_I1_WATTS)
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return -ENODEV;
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*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
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SF_CURR, POWER_SETUP_I1_SHIFT);
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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}
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static int
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xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, long val)
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{
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u32 uval;
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switch (attr) {
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case hwmon_curr_crit:
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uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_CURR);
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return xe_hwmon_pcode_write_i1(hwmon->gt, uval);
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default:
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return -EOPNOTSUPP;
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}
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@ -238,6 +332,9 @@ xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
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case hwmon_power:
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ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
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break;
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case hwmon_curr:
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ret = xe_hwmon_curr_is_visible(hwmon, attr);
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break;
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default:
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ret = 0;
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break;
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@ -261,6 +358,9 @@ xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
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case hwmon_power:
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ret = xe_hwmon_power_read(hwmon, attr, channel, val);
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break;
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case hwmon_curr:
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ret = xe_hwmon_curr_read(hwmon, attr, val);
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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@ -284,6 +384,9 @@ xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
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case hwmon_power:
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ret = xe_hwmon_power_write(hwmon, attr, channel, val);
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break;
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case hwmon_curr:
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ret = xe_hwmon_curr_write(hwmon, attr, val);
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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@ -22,4 +22,9 @@ int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 val,
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int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,
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u32 reply_mask, u32 reply, int timeout_ms);
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#define PCODE_MBOX(mbcmd, param1, param2)\
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(FIELD_PREP(PCODE_MB_COMMAND, mbcmd)\
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| FIELD_PREP(PCODE_MB_PARAM1, param1)\
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| FIELD_PREP(PCODE_MB_PARAM2, param2))
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#endif
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@ -35,6 +35,13 @@
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#define DGFX_GET_INIT_STATUS 0x0
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#define DGFX_INIT_STATUS_COMPLETE 0x1
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#define PCODE_POWER_SETUP 0x7C
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#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
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#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
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#define POWER_SETUP_I1_WATTS REG_BIT(31)
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#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
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#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
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struct pcode_err_decode {
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int errno;
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const char *str;
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