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mmc: sdhci_am654: Update OTAPDLY writes
According to the latest AM65x Data Manual[1], a different output tap delay value is optimum for a given speed mode. Therefore, deprecate the ti,otap-del-sel binding and introduce a new binding for each of the possible MMC/SD speed modes. If the legacy mode is not found, fall back to old binding to maintain dts compatibility. [1] http://www.ti.com/lit/gpn/am6526 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108150920.14547-3-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Faiz Abbas
Ulf Hansson
parent
70fd681e7e
commit
8ee5fc0e0b
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@ -81,7 +81,8 @@ static struct regmap_config sdhci_am654_regmap_config = {
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struct sdhci_am654_data {
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struct regmap *base;
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int otap_del_sel;
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bool legacy_otapdly;
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int otap_del_sel[11];
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int trm_icp;
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int drv_strength;
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bool dll_on;
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@ -98,11 +99,34 @@ struct sdhci_am654_driver_data {
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#define DLL_PRESENT (1 << 3)
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};
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struct timing_data {
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const char *binding;
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u32 capability;
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};
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static const struct timing_data td[] = {
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[MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0},
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[MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED},
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[MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED},
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[MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12},
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[MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25},
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[MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50},
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[MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
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MMC_CAP_UHS_SDR104},
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[MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50},
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[MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR},
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[MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200},
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[MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400},
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};
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static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
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unsigned char timing = host->mmc->ios.timing;
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int sel50, sel100, freqsel;
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u32 otap_del_sel;
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u32 otap_del_ena;
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u32 mask, val;
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int ret;
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@ -116,22 +140,29 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
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if (clock > CLOCK_TOO_SLOW_HZ) {
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/* Setup DLL Output TAP delay */
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (1 << OTAPDLYENA_SHIFT) |
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(sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
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/* Write to STRBSEL for HS400 speed mode */
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if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
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if (sdhci_am654->flags & STRBSEL_4_BIT)
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mask = STRBSEL_4BIT_MASK;
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else
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mask = STRBSEL_8BIT_MASK;
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if (sdhci_am654->legacy_otapdly)
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otap_del_sel = sdhci_am654->otap_del_sel[0];
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else
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otap_del_sel = sdhci_am654->otap_del_sel[timing];
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask,
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sdhci_am654->strb_sel <<
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STRBSEL_SHIFT);
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otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (otap_del_ena << OTAPDLYENA_SHIFT) |
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(otap_del_sel << OTAPDLYSEL_SHIFT);
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/* Write to STRBSEL for HS400 speed mode */
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if (timing == MMC_TIMING_MMC_HS400) {
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if (sdhci_am654->flags & STRBSEL_4_BIT)
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mask |= STRBSEL_4BIT_MASK;
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else
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mask |= STRBSEL_8BIT_MASK;
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val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
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}
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
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if (sdhci_am654->flags & FREQSEL_2_BIT) {
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switch (clock) {
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case 200000000:
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@ -198,11 +229,19 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
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int val, mask;
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unsigned char timing = host->mmc->ios.timing;
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u32 otap_del_sel;
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u32 mask, val;
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/* Setup DLL Output TAP delay */
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if (sdhci_am654->legacy_otapdly)
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otap_del_sel = sdhci_am654->otap_del_sel[0];
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else
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otap_del_sel = sdhci_am654->otap_del_sel[timing];
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (1 << OTAPDLYENA_SHIFT) |
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(sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
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val = (0x1 << OTAPDLYENA_SHIFT) |
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(otap_del_sel << OTAPDLYSEL_SHIFT);
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regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
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sdhci_set_clock(host, clock);
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@ -371,6 +410,55 @@ static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
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return ret;
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}
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static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
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struct sdhci_am654_data *sdhci_am654)
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{
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struct device *dev = mmc_dev(host->mmc);
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int i;
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int ret;
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ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].binding,
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&sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
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if (ret) {
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/*
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* ti,otap-del-sel-legacy is mandatory, look for old binding
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* if not found.
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*/
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ret = device_property_read_u32(dev, "ti,otap-del-sel",
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&sdhci_am654->otap_del_sel[0]);
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if (ret) {
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dev_err(dev, "Couldn't find otap-del-sel\n");
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return ret;
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}
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dev_info(dev, "Using legacy binding ti,otap-del-sel\n");
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sdhci_am654->legacy_otapdly = true;
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return 0;
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}
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for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) {
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ret = device_property_read_u32(dev, td[i].binding,
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&sdhci_am654->otap_del_sel[i]);
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if (ret) {
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dev_dbg(dev, "Couldn't find %s\n",
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td[i].binding);
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/*
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* Remove the corresponding capability
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* if an otap-del-sel value is not found
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*/
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if (i <= MMC_TIMING_MMC_DDR52)
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host->mmc->caps &= ~td[i].capability;
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else
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host->mmc->caps2 &= ~td[i].capability;
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}
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}
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return 0;
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}
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static int sdhci_am654_init(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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@ -419,6 +507,10 @@ static int sdhci_am654_init(struct sdhci_host *host)
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if (ret)
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goto err_cleanup_host;
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ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
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if (ret)
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goto err_cleanup_host;
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ret = __sdhci_add_host(host);
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if (ret)
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goto err_cleanup_host;
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@ -437,11 +529,6 @@ static int sdhci_am654_get_of_property(struct platform_device *pdev,
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int drv_strength;
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int ret;
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ret = device_property_read_u32(dev, "ti,otap-del-sel",
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&sdhci_am654->otap_del_sel);
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if (ret)
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return ret;
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if (sdhci_am654->flags & DLL_PRESENT) {
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ret = device_property_read_u32(dev, "ti,trm-icp",
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&sdhci_am654->trm_icp);
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@ -322,6 +322,8 @@ struct mmc_host {
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#define MMC_CAP_3_3V_DDR (1 << 11) /* Host supports eMMC DDR 3.3V */
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#define MMC_CAP_1_8V_DDR (1 << 12) /* Host supports eMMC DDR 1.8V */
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#define MMC_CAP_1_2V_DDR (1 << 13) /* Host supports eMMC DDR 1.2V */
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#define MMC_CAP_DDR (MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | \
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MMC_CAP_1_2V_DDR)
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#define MMC_CAP_POWER_OFF_CARD (1 << 14) /* Can power off after boot */
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#define MMC_CAP_BUS_WIDTH_TEST (1 << 15) /* CMD14/CMD19 bus width ok */
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#define MMC_CAP_UHS_SDR12 (1 << 16) /* Host supports UHS SDR12 mode */
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