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https://github.com/torvalds/linux
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ARC: cacheflush: move some code around, delete old comments
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
8362c389a4
commit
8ea2ddff41
1 changed files with 102 additions and 165 deletions
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@ -1,64 +1,12 @@
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/*
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* ARC700 VIPT Cache Management
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* ARC Cache Management
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*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
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* -flush_cache_dup_mm (fork)
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* -likewise for flush_cache_mm (exit/execve)
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* -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break)
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*
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* vineetg: Apr 2011
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* -Now that MMU can support larger pg sz (16K), the determiniation of
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* aliasing shd not be based on assumption of 8k pg
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*
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* vineetg: Mar 2011
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* -optimised version of flush_icache_range( ) for making I/D coherent
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* when vaddr is available (agnostic of num of aliases)
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*
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* vineetg: Mar 2011
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* -Added documentation about I-cache aliasing on ARC700 and the way it
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* was handled up until MMU V2.
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* -Spotted a three year old bug when killing the 4 aliases, which needs
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* bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03}
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* instead of paddr | {0x00, 0x01, 0x10, 0x11}
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* (Rajesh you owe me one now)
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*
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* vineetg: Dec 2010
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* -Off-by-one error when computing num_of_lines to flush
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* This broke signal handling with bionic which uses synthetic sigret stub
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*
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* vineetg: Mar 2010
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* -GCC can't generate ZOL for core cache flush loops.
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* Conv them into iterations based as opposed to while (start < end) types
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*
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* Vineetg: July 2009
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* -In I-cache flush routine we used to chk for aliasing for every line INV.
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* Instead now we setup routines per cache geometry and invoke them
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* via function pointers.
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*
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* Vineetg: Jan 2009
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* -Cache Line flush routines used to flush an extra line beyond end addr
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* because check was while (end >= start) instead of (end > start)
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* =Some call sites had to work around by doing -1, -4 etc to end param
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* =Some callers didnt care. This was spec bad in case of INV routines
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* which would discard valid data (cause of the horrible ext2 bug
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* in ARC IDE driver)
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*
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* vineetg: June 11th 2008: Fixed flush_icache_range( )
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* -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need
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* to be flushed, which it was not doing.
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* -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API,
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* however ARC cache maintenance OPs require PHY addr. Thus need to do
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* vmalloc_to_phy.
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* -Also added optimisation there, that for range > PAGE SIZE we flush the
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* entire cache in one shot rather than line by line. For e.g. a module
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* with Code sz 600k, old code flushed 600k worth of cache (line-by-line),
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* while cache is only 16 or 32k.
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*/
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#include <linux/module.h>
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@ -142,54 +90,8 @@ void read_decode_cache_bcr(void)
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}
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/*
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* 1. Validate the Cache Geomtery (compile time config matches hardware)
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* 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn)
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* (aliasing D-cache configurations are not supported YET)
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* 3. Enable the Caches, setup default flush mode for D-Cache
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* 3. Calculate the SHMLBA used by user space
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* Line Operation on {I,D}-Cache
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*/
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void arc_cache_init(void)
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{
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unsigned int __maybe_unused cpu = smp_processor_id();
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char str[256];
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printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
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if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
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struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
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if (!ic->ver)
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panic("cache support enabled but non-existent cache\n");
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if (ic->line_len != L1_CACHE_BYTES)
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panic("ICache line [%d] != kernel Config [%d]",
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ic->line_len, L1_CACHE_BYTES);
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if (ic->ver != CONFIG_ARC_MMU_VER)
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panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
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ic->ver, CONFIG_ARC_MMU_VER);
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}
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if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {
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struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
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int handled;
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if (!dc->ver)
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panic("cache support enabled but non-existent cache\n");
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if (dc->line_len != L1_CACHE_BYTES)
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panic("DCache line [%d] != kernel Config [%d]",
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dc->line_len, L1_CACHE_BYTES);
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/* check for D-Cache aliasing */
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handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
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if (dc->alias && !handled)
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panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
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else if (!dc->alias && handled)
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panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
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}
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}
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#define OP_INV 0x1
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#define OP_FLUSH 0x2
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@ -197,16 +99,55 @@ void arc_cache_init(void)
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#define OP_INV_IC 0x4
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/*
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* Common Helper for Line Operations on {I,D}-Cache
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* I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3)
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*
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* ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
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* The orig Cache Management Module "CDU" only required paddr to invalidate a
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* certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
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* Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
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* the exact same line.
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*
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* However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
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* paddr alone could not be used to correctly index the cache.
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*
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* ------------------
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* MMU v1/v2 (Fixed Page Size 8k)
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* ------------------
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* The solution was to provide CDU with these additonal vaddr bits. These
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* would be bits [x:13], x would depend on cache-geometry, 13 comes from
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* standard page size of 8k.
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* H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
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* of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
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* orig 5 bits of paddr were anyways ignored by CDU line ops, as they
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* represent the offset within cache-line. The adv of using this "clumsy"
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* interface for additional info was no new reg was needed in CDU programming
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* model.
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*
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* 17:13 represented the max num of bits passable, actual bits needed were
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* fewer, based on the num-of-aliases possible.
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* -for 2 alias possibility, only bit 13 needed (32K cache)
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* -for 4 alias possibility, bits 14:13 needed (64K cache)
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*
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* ------------------
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* MMU v3
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* ------------------
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* This ver of MMU supports variable page sizes (1k-16k): although Linux will
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* only support 8k (default), 16k and 4k.
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* However from hardware perspective, smaller page sizes aggrevate aliasing
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* meaning more vaddr bits needed to disambiguate the cache-line-op ;
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* the existing scheme of piggybacking won't work for certain configurations.
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* Two new registers IC_PTAG and DC_PTAG inttoduced.
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* "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
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*/
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static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr,
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unsigned long sz, const int cacheop)
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unsigned long sz, const int op)
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{
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unsigned int aux_cmd, aux_tag;
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int num_lines;
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const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE;
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if (cacheop == OP_INV_IC) {
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if (op == OP_INV_IC) {
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aux_cmd = ARC_REG_IC_IVIL;
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#if (CONFIG_ARC_MMU_VER > 2)
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aux_tag = ARC_REG_IC_PTAG;
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@ -214,7 +155,7 @@ static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr,
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}
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else {
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/* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
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aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
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aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
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#if (CONFIG_ARC_MMU_VER > 2)
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aux_tag = ARC_REG_DC_PTAG;
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#endif
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@ -296,107 +237,60 @@ static inline void __after_dc_op(const int op, unsigned int reg)
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/*
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* Operation on Entire D-Cache
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* @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
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* @op = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
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* Note that constant propagation ensures all the checks are gone
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* in generated code
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*/
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static inline void __dc_entire_op(const int cacheop)
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static inline void __dc_entire_op(const int op)
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{
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unsigned int ctrl_reg;
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int aux;
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ctrl_reg = __before_dc_op(cacheop);
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ctrl_reg = __before_dc_op(op);
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if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
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if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
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aux = ARC_REG_DC_IVDC;
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else
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aux = ARC_REG_DC_FLSH;
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write_aux_reg(aux, 0x1);
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__after_dc_op(cacheop, ctrl_reg);
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__after_dc_op(op, ctrl_reg);
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}
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/* For kernel mappings cache operation: index is same as paddr */
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#define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
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/*
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* D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback)
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* D-Cache Line ops: Per Line INV (discard or wback+discard) or FLUSH (wback)
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*/
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static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr,
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unsigned long sz, const int cacheop)
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unsigned long sz, const int op)
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{
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unsigned long flags;
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unsigned int ctrl_reg;
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local_irq_save(flags);
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ctrl_reg = __before_dc_op(cacheop);
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ctrl_reg = __before_dc_op(op);
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__cache_line_loop(paddr, vaddr, sz, cacheop);
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__cache_line_loop(paddr, vaddr, sz, op);
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__after_dc_op(cacheop, ctrl_reg);
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__after_dc_op(op, ctrl_reg);
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local_irq_restore(flags);
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}
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#else
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#define __dc_entire_op(cacheop)
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#define __dc_line_op(paddr, vaddr, sz, cacheop)
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#define __dc_line_op_k(paddr, sz, cacheop)
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#define __dc_entire_op(op)
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#define __dc_line_op(paddr, vaddr, sz, op)
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#define __dc_line_op_k(paddr, sz, op)
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#endif /* CONFIG_ARC_HAS_DCACHE */
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#ifdef CONFIG_ARC_HAS_ICACHE
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/*
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* I-Cache Aliasing in ARC700 VIPT caches
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*
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* ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
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* The orig Cache Management Module "CDU" only required paddr to invalidate a
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* certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
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* Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
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* the exact same line.
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*
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* However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
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* paddr alone could not be used to correctly index the cache.
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*
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* ------------------
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* MMU v1/v2 (Fixed Page Size 8k)
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* ------------------
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* The solution was to provide CDU with these additonal vaddr bits. These
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* would be bits [x:13], x would depend on cache-geometry, 13 comes from
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* standard page size of 8k.
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* H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
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* of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
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* orig 5 bits of paddr were anyways ignored by CDU line ops, as they
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* represent the offset within cache-line. The adv of using this "clumsy"
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* interface for additional info was no new reg was needed in CDU programming
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* model.
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*
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* 17:13 represented the max num of bits passable, actual bits needed were
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* fewer, based on the num-of-aliases possible.
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* -for 2 alias possibility, only bit 13 needed (32K cache)
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* -for 4 alias possibility, bits 14:13 needed (64K cache)
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*
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* ------------------
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* MMU v3
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* ------------------
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* This ver of MMU supports variable page sizes (1k-16k): although Linux will
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* only support 8k (default), 16k and 4k.
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* However from hardware perspective, smaller page sizes aggrevate aliasing
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* meaning more vaddr bits needed to disambiguate the cache-line-op ;
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* the existing scheme of piggybacking won't work for certain configurations.
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* Two new registers IC_PTAG and DC_PTAG inttoduced.
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* "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
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*/
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/***********************************************************
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* Machine specific helper for per line I-Cache invalidate.
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*/
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static inline void __ic_entire_inv(void)
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{
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write_aux_reg(ARC_REG_IC_IVIC, 1);
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@ -721,3 +615,46 @@ SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
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flush_cache_all();
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return 0;
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}
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void arc_cache_init(void)
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{
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unsigned int __maybe_unused cpu = smp_processor_id();
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char str[256];
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printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
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if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
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struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
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if (!ic->ver)
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panic("cache support enabled but non-existent cache\n");
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if (ic->line_len != L1_CACHE_BYTES)
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panic("ICache line [%d] != kernel Config [%d]",
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ic->line_len, L1_CACHE_BYTES);
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if (ic->ver != CONFIG_ARC_MMU_VER)
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panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
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ic->ver, CONFIG_ARC_MMU_VER);
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}
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if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {
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struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
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int handled;
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if (!dc->ver)
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panic("cache support enabled but non-existent cache\n");
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if (dc->line_len != L1_CACHE_BYTES)
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panic("DCache line [%d] != kernel Config [%d]",
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dc->line_len, L1_CACHE_BYTES);
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/* check for D-Cache aliasing */
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handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
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if (dc->alias && !handled)
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panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
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else if (!dc->alias && handled)
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panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
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}
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}
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