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soc: mediatek: svs: Add support for MT8195 SoC
MT8195 svs gpu uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Mark Tseng <chun-jen.tseng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Mark Tseng
AngeloGioacchino Del Regno
parent
b85ea95d08
commit
8ccda5ceca
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@ -1792,6 +1792,75 @@ static int svs_get_efuse_data(struct svs_platform *svsp,
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return 0;
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}
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static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp)
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{
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struct svs_bank *svsb;
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u32 idx, i, ft_pgm, vmin, golden_temp;
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int ret;
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for (i = 0; i < svsp->efuse_max; i++)
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if (svsp->efuse[i])
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dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
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i, svsp->efuse[i]);
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if (!svsp->efuse[10]) {
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dev_notice(svsp->dev, "svs_efuse[10] = 0x0?\n");
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return false;
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}
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/* Svs efuse parsing */
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ft_pgm = svsp->efuse[0] & GENMASK(7, 0);
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vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0);
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for (idx = 0; idx < svsp->bank_max; idx++) {
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svsb = &svsp->banks[idx];
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if (vmin == 0x1)
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svsb->vmin = 0x1e;
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if (ft_pgm == 0)
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svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
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if (svsb->type == SVSB_LOW) {
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svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0);
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svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0);
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svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0);
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svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0);
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svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0);
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} else if (svsb->type == SVSB_HIGH) {
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svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0);
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svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0);
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svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0);
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svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0);
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svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0);
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}
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svsb->vmax += svsb->dvt_fixed;
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}
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ret = svs_get_efuse_data(svsp, "t-calibration-data",
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&svsp->tefuse, &svsp->tefuse_max);
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if (ret)
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return false;
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for (i = 0; i < svsp->tefuse_max; i++)
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if (svsp->tefuse[i] != 0)
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break;
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if (i == svsp->tefuse_max)
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golden_temp = 50; /* All thermal efuse data are 0 */
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else
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golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0);
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for (idx = 0; idx < svsp->bank_max; idx++) {
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svsb = &svsp->banks[idx];
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svsb->mts = 500;
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svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4;
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}
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return true;
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}
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static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp)
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{
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struct svs_bank *svsb;
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@ -2222,6 +2291,61 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp)
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return 0;
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}
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static struct svs_bank svs_mt8195_banks[] = {
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{
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.sw_id = SVSB_GPU,
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.type = SVSB_LOW,
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.set_freq_pct = svs_set_bank_freq_pct_v3,
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.get_volts = svs_get_bank_volts_v3,
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.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT,
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.mode_support = SVSB_MODE_INIT02,
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.opp_count = MAX_OPP_ENTRIES,
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.freq_base = 640000000,
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.turn_freq_base = 640000000,
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.volt_step = 6250,
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.volt_base = 400000,
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.vmax = 0x38,
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.vmin = 0x14,
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.age_config = 0x555555,
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.dc_config = 0x1,
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.dvt_fixed = 0x1,
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.vco = 0x18,
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.chk_shift = 0x87,
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.core_sel = 0x0fff0100,
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.int_st = BIT(0),
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.ctl0 = 0x00540003,
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},
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{
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.sw_id = SVSB_GPU,
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.type = SVSB_HIGH,
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.set_freq_pct = svs_set_bank_freq_pct_v3,
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.get_volts = svs_get_bank_volts_v3,
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.tzone_name = "gpu1",
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.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT |
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SVSB_MON_VOLT_IGNORE,
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.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
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.opp_count = MAX_OPP_ENTRIES,
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.freq_base = 880000000,
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.turn_freq_base = 640000000,
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.volt_step = 6250,
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.volt_base = 400000,
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.vmax = 0x38,
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.vmin = 0x14,
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.age_config = 0x555555,
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.dc_config = 0x1,
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.dvt_fixed = 0x6,
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.vco = 0x18,
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.chk_shift = 0x87,
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.core_sel = 0x0fff0101,
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.int_st = BIT(1),
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.ctl0 = 0x00540003,
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.tzone_htemp = 85000,
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.tzone_htemp_voffset = 0,
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.tzone_ltemp = 25000,
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.tzone_ltemp_voffset = 7,
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},
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};
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static struct svs_bank svs_mt8192_banks[] = {
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{
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.sw_id = SVSB_GPU,
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@ -2441,6 +2565,15 @@ static struct svs_bank svs_mt8183_banks[] = {
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},
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};
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static const struct svs_platform_data svs_mt8195_platform_data = {
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.name = "mt8195-svs",
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.banks = svs_mt8195_banks,
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.efuse_parsing = svs_mt8195_efuse_parsing,
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.probe = svs_mt8192_platform_probe,
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.regs = svs_regs_v2,
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.bank_max = ARRAY_SIZE(svs_mt8195_banks),
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};
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static const struct svs_platform_data svs_mt8192_platform_data = {
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.name = "mt8192-svs",
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.banks = svs_mt8192_banks,
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@ -2470,6 +2603,9 @@ static const struct svs_platform_data svs_mt8183_platform_data = {
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static const struct of_device_id svs_of_match[] = {
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{
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.compatible = "mediatek,mt8195-svs",
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.data = &svs_mt8195_platform_data,
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}, {
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.compatible = "mediatek,mt8192-svs",
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.data = &svs_mt8192_platform_data,
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}, {
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