Merge branch 'aquantia-fixes'

Igor Russkikh says:

====================
Aquantia/Marvell AQtion atlantic driver fixes 10/2019

Here is a set of various bugfixes, to be considered for stable as well.

V2: double space removed
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2019-10-14 17:01:53 -07:00
commit 8c16b55bbf
8 changed files with 77 additions and 30 deletions

View file

@ -194,9 +194,7 @@ static void aq_ndev_set_multicast_settings(struct net_device *ndev)
{ {
struct aq_nic_s *aq_nic = netdev_priv(ndev); struct aq_nic_s *aq_nic = netdev_priv(ndev);
aq_nic_set_packet_filter(aq_nic, ndev->flags); (void)aq_nic_set_multicast_list(aq_nic, ndev);
aq_nic_set_multicast_list(aq_nic, ndev);
} }
static int aq_ndo_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, static int aq_ndo_vlan_rx_add_vid(struct net_device *ndev, __be16 proto,

View file

@ -631,9 +631,12 @@ int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags)
int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev) int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev)
{ {
unsigned int packet_filter = self->packet_filter; const struct aq_hw_ops *hw_ops = self->aq_hw_ops;
struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
unsigned int packet_filter = ndev->flags;
struct netdev_hw_addr *ha = NULL; struct netdev_hw_addr *ha = NULL;
unsigned int i = 0U; unsigned int i = 0U;
int err = 0;
self->mc_list.count = 0; self->mc_list.count = 0;
if (netdev_uc_count(ndev) > AQ_HW_MULTICAST_ADDRESS_MAX) { if (netdev_uc_count(ndev) > AQ_HW_MULTICAST_ADDRESS_MAX) {
@ -641,29 +644,26 @@ int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev)
} else { } else {
netdev_for_each_uc_addr(ha, ndev) { netdev_for_each_uc_addr(ha, ndev) {
ether_addr_copy(self->mc_list.ar[i++], ha->addr); ether_addr_copy(self->mc_list.ar[i++], ha->addr);
if (i >= AQ_HW_MULTICAST_ADDRESS_MAX)
break;
} }
} }
if (i + netdev_mc_count(ndev) > AQ_HW_MULTICAST_ADDRESS_MAX) { cfg->is_mc_list_enabled = !!(packet_filter & IFF_MULTICAST);
packet_filter |= IFF_ALLMULTI; if (cfg->is_mc_list_enabled) {
} else { if (i + netdev_mc_count(ndev) > AQ_HW_MULTICAST_ADDRESS_MAX) {
netdev_for_each_mc_addr(ha, ndev) { packet_filter |= IFF_ALLMULTI;
ether_addr_copy(self->mc_list.ar[i++], ha->addr); } else {
netdev_for_each_mc_addr(ha, ndev) {
if (i >= AQ_HW_MULTICAST_ADDRESS_MAX) ether_addr_copy(self->mc_list.ar[i++],
break; ha->addr);
}
} }
} }
if (i > 0 && i <= AQ_HW_MULTICAST_ADDRESS_MAX) { if (i > 0 && i <= AQ_HW_MULTICAST_ADDRESS_MAX) {
packet_filter |= IFF_MULTICAST;
self->mc_list.count = i; self->mc_list.count = i;
self->aq_hw_ops->hw_multicast_list_set(self->aq_hw, err = hw_ops->hw_multicast_list_set(self->aq_hw,
self->mc_list.ar, self->mc_list.ar,
self->mc_list.count); self->mc_list.count);
} }
return aq_nic_set_packet_filter(self, packet_filter); return aq_nic_set_packet_filter(self, packet_filter);
} }

View file

@ -313,6 +313,7 @@ int aq_ring_rx_clean(struct aq_ring_s *self,
break; break;
buff->is_error |= buff_->is_error; buff->is_error |= buff_->is_error;
buff->is_cso_err |= buff_->is_cso_err;
} while (!buff_->is_eop); } while (!buff_->is_eop);
@ -320,7 +321,7 @@ int aq_ring_rx_clean(struct aq_ring_s *self,
err = 0; err = 0;
goto err_exit; goto err_exit;
} }
if (buff->is_error) { if (buff->is_error || buff->is_cso_err) {
buff_ = buff; buff_ = buff;
do { do {
next_ = buff_->next, next_ = buff_->next,

View file

@ -818,14 +818,15 @@ static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
cfg->is_vlan_force_promisc); cfg->is_vlan_force_promisc);
hw_atl_rpfl2multicast_flr_en_set(self, hw_atl_rpfl2multicast_flr_en_set(self,
IS_FILTER_ENABLED(IFF_ALLMULTI), 0); IS_FILTER_ENABLED(IFF_ALLMULTI) &&
IS_FILTER_ENABLED(IFF_MULTICAST), 0);
hw_atl_rpfl2_accept_all_mc_packets_set(self, hw_atl_rpfl2_accept_all_mc_packets_set(self,
IS_FILTER_ENABLED(IFF_ALLMULTI)); IS_FILTER_ENABLED(IFF_ALLMULTI) &&
IS_FILTER_ENABLED(IFF_MULTICAST));
hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST)); hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i) for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
hw_atl_rpfl2_uc_flr_en_set(self, hw_atl_rpfl2_uc_flr_en_set(self,
@ -968,14 +969,26 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
static int hw_atl_b0_hw_stop(struct aq_hw_s *self) static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
{ {
int err;
u32 val;
hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK); hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
/* Invalidate Descriptor Cache to prevent writing to the cached /* Invalidate Descriptor Cache to prevent writing to the cached
* descriptors and to the data pointer of those descriptors * descriptors and to the data pointer of those descriptors
*/ */
hw_atl_rdm_rx_dma_desc_cache_init_set(self, 1); hw_atl_rdm_rx_dma_desc_cache_init_tgl(self);
return aq_hw_err_from_flags(self); err = aq_hw_err_from_flags(self);
if (err)
goto err_exit;
readx_poll_timeout_atomic(hw_atl_rdm_rx_dma_desc_cache_init_done_get,
self, val, val == 1, 1000U, 10000U);
err_exit:
return err;
} }
static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,

View file

@ -606,12 +606,25 @@ void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode
HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode); HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
} }
void hw_atl_rdm_rx_dma_desc_cache_init_set(struct aq_hw_s *aq_hw, u32 init) void hw_atl_rdm_rx_dma_desc_cache_init_tgl(struct aq_hw_s *aq_hw)
{ {
u32 val;
val = aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT);
aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR, aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT,
init); val ^ 1);
}
u32 hw_atl_rdm_rx_dma_desc_cache_init_done_get(struct aq_hw_s *aq_hw)
{
return aq_hw_read_reg_bit(aq_hw, RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR,
RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK,
RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT);
} }
void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,

View file

@ -313,8 +313,11 @@ void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
u32 rx_pkt_buff_size_per_tc, u32 rx_pkt_buff_size_per_tc,
u32 buffer); u32 buffer);
/* set rdm rx dma descriptor cache init */ /* toggle rdm rx dma descriptor cache init */
void hw_atl_rdm_rx_dma_desc_cache_init_set(struct aq_hw_s *aq_hw, u32 init); void hw_atl_rdm_rx_dma_desc_cache_init_tgl(struct aq_hw_s *aq_hw);
/* get rdm rx dma descriptor cache init done */
u32 hw_atl_rdm_rx_dma_desc_cache_init_done_get(struct aq_hw_s *aq_hw);
/* set rx xoff enable (per tc) */ /* set rx xoff enable (per tc) */
void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc, void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,

View file

@ -318,6 +318,25 @@
/* default value of bitfield rdm_desc_init_i */ /* default value of bitfield rdm_desc_init_i */
#define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT 0x0 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT 0x0
/* rdm_desc_init_done_i bitfield definitions
* preprocessor definitions for the bitfield rdm_desc_init_done_i.
* port="pif_rdm_desc_init_done_i"
*/
/* register address for bitfield rdm_desc_init_done_i */
#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR 0x00005a10
/* bitmask for bitfield rdm_desc_init_done_i */
#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK 0x00000001U
/* inverted bitmask for bitfield rdm_desc_init_done_i */
#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSKN 0xfffffffe
/* lower bit position of bitfield rdm_desc_init_done_i */
#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT 0U
/* width of bitfield rdm_desc_init_done_i */
#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_WIDTH 1
/* default value of bitfield rdm_desc_init_done_i */
#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_DEFAULT 0x0
/* rx int_desc_wrb_en bitfield definitions /* rx int_desc_wrb_en bitfield definitions
* preprocessor definitions for the bitfield "int_desc_wrb_en". * preprocessor definitions for the bitfield "int_desc_wrb_en".
* port="pif_rdm_int_desc_wrb_en_i" * port="pif_rdm_int_desc_wrb_en_i"

View file

@ -337,7 +337,7 @@ static int aq_fw2x_get_phy_temp(struct aq_hw_s *self, int *temp)
/* Convert PHY temperature from 1/256 degree Celsius /* Convert PHY temperature from 1/256 degree Celsius
* to 1/1000 degree Celsius. * to 1/1000 degree Celsius.
*/ */
*temp = temp_res * 1000 / 256; *temp = (temp_res & 0xFFFF) * 1000 / 256;
return 0; return 0;
} }