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https://github.com/torvalds/linux
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nvme updates for Linux 5.19
- set non-mdts limits in nvme_scan_work (Chaitanya Kulkarni) - add support for TP4084 - Time-to-Ready Enhancements (me) -----BEGIN PGP SIGNATURE----- iQI/BAABCgApFiEEgdbnc3r/njty3Iq9D55TZVIEUYMFAmKGnjgLHGhjaEBsc3Qu ZGUACgkQD55TZVIEUYPxSA//XaYH0kncX2znto5S6772TJ64L2Rtfbh7LPQzE40V /Au3OvEESyP/oGh7RQxTMdKnU19Gzc+lYzTZ8VP3h/cORVEtHb5RSzb2UEUWyRbm 3+WEurG6d91PlH0HyfUsRe1y441pwr6WVDb3Zh/O1/PhsM0RihjnLEjdjobQMQJL BKFPpEfOxBPFDaaHEAVM8SB0wkhAD17C8C+YPow8IF4F1iBqmjpgtjixtHBmAovu 0Uq99ySyypyjPsEYPrUHesNFmOP4FJbosBvLVJuHDrOVdl900PmWhbCjsOcfzVRn g7xpYxreStHFUsneA8GkfUM6gEVMhOpTjdeborv9P64O9oziH35ZENHorHf+QCAu Es0HGJ3QziWqchkWxFxzLJWB4Ab5j0hhBNocQB4aM6lb8sV82+Fcyxf7NOMIkJIo aFlHXRdm6d3Ox/hBJiERFmb52Op3KAvrTYyhpPFGhQRdptAf3p1IQCfUykl5mIXz KW5BhonVtY/jS/lqbe5bw08becIqlcaX9+4QbxHGHaQO7tBRewBPMmbWfIs4Nh9i OytRRqiF/jigL66C6+wZR8bvnyk1kKvJvfUJDBv2s0THPqfqG55uYkDfZsX+B3nV n8KF4xRoLwbqIhkDRdnrhYbFaRwsK7S6hEa8nHLsUR+Ue1lc9rzOJmnbSHgXALWg VeA= =6fdL -----END PGP SIGNATURE----- Merge tag 'nvme-5.19-2022-05-19' of git://git.infradead.org/nvme into for-5.19/drivers Pull NVMe updates from Christoph: "nvme updates for Linux 5.19 - set non-mdts limits in nvme_scan_work (Chaitanya Kulkarni) - add support for TP4084 - Time-to-Ready Enhancements (me)" * tag 'nvme-5.19-2022-05-19' of git://git.infradead.org/nvme: nvme: set non-mdts limits in nvme_scan_work nvme: add support for TP4084 - Time-to-Ready Enhancements
This commit is contained in:
Jens Axboe
commit
8ad9f57755
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@ -91,6 +91,7 @@ static const char * const nvme_statuses[] = {
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[NVME_SC_NS_WRITE_PROTECTED] = "Namespace is Write Protected",
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[NVME_SC_CMD_INTERRUPTED] = "Command Interrupted",
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[NVME_SC_TRANSIENT_TR_ERR] = "Transient Transport Error",
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[NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY] = "Admin Command Media Not Ready",
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[NVME_SC_INVALID_IO_CMD_SET] = "Invalid IO Command Set",
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[NVME_SC_LBA_RANGE] = "LBA Out of Range",
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[NVME_SC_CAP_EXCEEDED] = "Capacity Exceeded",
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@ -1427,6 +1427,32 @@ static int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid,
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return error;
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}
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static int nvme_identify_ns_cs_indep(struct nvme_ctrl *ctrl, unsigned nsid,
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struct nvme_id_ns_cs_indep **id)
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{
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struct nvme_command c = {
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.identify.opcode = nvme_admin_identify,
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.identify.nsid = cpu_to_le32(nsid),
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.identify.cns = NVME_ID_CNS_NS_CS_INDEP,
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};
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int ret;
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*id = kmalloc(sizeof(**id), GFP_KERNEL);
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if (!*id)
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return -ENOMEM;
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ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id));
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if (ret) {
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dev_warn(ctrl->device,
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"Identify namespace (CS independent) failed (%d)\n",
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ret);
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kfree(*id);
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return ret;
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}
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return 0;
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}
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static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid,
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unsigned int dword11, void *buffer, size_t buflen, u32 *result)
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{
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@ -2103,10 +2129,9 @@ static const struct block_device_operations nvme_bdev_ops = {
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.pr_ops = &nvme_pr_ops,
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};
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static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
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static int nvme_wait_ready(struct nvme_ctrl *ctrl, u32 timeout, bool enabled)
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{
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unsigned long timeout =
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((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
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unsigned long timeout_jiffies = ((timeout + 1) * HZ / 2) + jiffies;
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u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
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int ret;
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@ -2119,7 +2144,7 @@ static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
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usleep_range(1000, 2000);
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if (fatal_signal_pending(current))
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return -EINTR;
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if (time_after(jiffies, timeout)) {
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if (time_after(jiffies, timeout_jiffies)) {
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dev_err(ctrl->device,
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"Device not ready; aborting %s, CSTS=0x%x\n",
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enabled ? "initialisation" : "reset", csts);
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@ -2150,13 +2175,14 @@ int nvme_disable_ctrl(struct nvme_ctrl *ctrl)
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if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
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msleep(NVME_QUIRK_DELAY_AMOUNT);
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return nvme_wait_ready(ctrl, ctrl->cap, false);
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return nvme_wait_ready(ctrl, NVME_CAP_TIMEOUT(ctrl->cap), false);
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}
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EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
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int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
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{
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unsigned dev_page_min;
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u32 timeout;
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int ret;
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ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
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@ -2177,6 +2203,27 @@ int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
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ctrl->ctrl_config = NVME_CC_CSS_CSI;
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else
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ctrl->ctrl_config = NVME_CC_CSS_NVM;
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if (ctrl->cap & NVME_CAP_CRMS_CRWMS) {
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u32 crto;
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ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CRTO, &crto);
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if (ret) {
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dev_err(ctrl->device, "Reading CRTO failed (%d)\n",
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ret);
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return ret;
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}
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if (ctrl->cap & NVME_CAP_CRMS_CRIMS) {
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ctrl->ctrl_config |= NVME_CC_CRIME;
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timeout = NVME_CRTO_CRIMT(crto);
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} else {
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timeout = NVME_CRTO_CRWMT(crto);
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}
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} else {
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timeout = NVME_CAP_TIMEOUT(ctrl->cap);
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}
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ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
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ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
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ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
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@ -2185,7 +2232,7 @@ int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
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ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
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if (ret)
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return ret;
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return nvme_wait_ready(ctrl, ctrl->cap, true);
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return nvme_wait_ready(ctrl, timeout, true);
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}
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EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
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@ -3082,10 +3129,6 @@ int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl)
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if (ret)
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return ret;
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ret = nvme_init_non_mdts_limits(ctrl);
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if (ret < 0)
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return ret;
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ret = nvme_configure_apst(ctrl);
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if (ret < 0)
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return ret;
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@ -4092,11 +4135,26 @@ static void nvme_validate_ns(struct nvme_ns *ns, struct nvme_ns_ids *ids)
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static void nvme_validate_or_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
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{
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struct nvme_ns_ids ids = { };
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struct nvme_id_ns_cs_indep *id;
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struct nvme_ns *ns;
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bool ready = true;
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if (nvme_identify_ns_descs(ctrl, nsid, &ids))
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return;
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/*
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* Check if the namespace is ready. If not ignore it, we will get an
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* AEN once it becomes ready and restart the scan.
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*/
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if ((ctrl->cap & NVME_CAP_CRMS_CRIMS) &&
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!nvme_identify_ns_cs_indep(ctrl, nsid, &id)) {
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ready = id->nstat & NVME_NSTAT_NRDY;
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kfree(id);
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}
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if (!ready)
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return;
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ns = nvme_find_get_ns(ctrl, nsid);
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if (ns) {
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nvme_validate_ns(ns, &ids);
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@ -4239,11 +4297,26 @@ static void nvme_scan_work(struct work_struct *work)
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{
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struct nvme_ctrl *ctrl =
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container_of(work, struct nvme_ctrl, scan_work);
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int ret;
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/* No tagset on a live ctrl means IO queues could not created */
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if (ctrl->state != NVME_CTRL_LIVE || !ctrl->tagset)
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return;
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/*
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* Identify controller limits can change at controller reset due to
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* new firmware download, even though it is not common we cannot ignore
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* such scenario. Controller's non-mdts limits are reported in the unit
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* of logical blocks that is dependent on the format of attached
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* namespace. Hence re-read the limits at the time of ns allocation.
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*/
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ret = nvme_init_non_mdts_limits(ctrl);
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if (ret < 0) {
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dev_warn(ctrl->device,
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"reading non-mdts-limits failed: %d\n", ret);
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return;
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}
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if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
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dev_info(ctrl->device, "rescanning namespaces.\n");
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nvme_clear_changed_ns_log(ctrl);
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@ -4841,6 +4914,8 @@ static inline void _nvme_check_size(void)
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BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
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BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
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BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
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BUILD_BUG_ON(sizeof(struct nvme_id_ns_cs_indep) !=
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NVME_IDENTIFY_DATA_SIZE);
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BUILD_BUG_ON(sizeof(struct nvme_id_ns_zns) != NVME_IDENTIFY_DATA_SIZE);
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BUILD_BUG_ON(sizeof(struct nvme_id_ns_nvm) != NVME_IDENTIFY_DATA_SIZE);
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BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_zns) != NVME_IDENTIFY_DATA_SIZE);
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@ -137,6 +137,7 @@ enum {
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NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
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* Space Control
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*/
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NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
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NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
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NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
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NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
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@ -161,6 +162,9 @@ enum {
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#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
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#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
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#define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
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#define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
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enum {
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NVME_CMBSZ_SQS = 1 << 0,
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NVME_CMBSZ_CQS = 1 << 1,
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@ -204,6 +208,7 @@ enum {
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NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
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NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
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NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
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NVME_CC_CRIME = 1 << 24,
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};
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enum {
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@ -227,6 +232,11 @@ enum {
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NVME_CAP_CSS_CSI = 1 << 6,
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};
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enum {
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NVME_CAP_CRMS_CRIMS = 1ULL << 59,
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NVME_CAP_CRMS_CRWMS = 1ULL << 60,
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};
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struct nvme_id_power_state {
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__le16 max_power; /* centiwatts */
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__u8 rsvd2;
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@ -414,6 +424,21 @@ struct nvme_id_ns {
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__u8 vs[3712];
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};
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/* I/O Command Set Independent Identify Namespace Data Structure */
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struct nvme_id_ns_cs_indep {
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__u8 nsfeat;
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__u8 nmic;
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__u8 rescap;
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__u8 fpi;
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__le32 anagrpid;
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__u8 nsattr;
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__u8 rsvd9;
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__le16 nvmsetid;
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__le16 endgid;
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__u8 nstat;
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__u8 rsvd15[4081];
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};
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struct nvme_zns_lbafe {
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__le64 zsze;
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__u8 zdes;
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@ -478,6 +503,7 @@ enum {
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NVME_ID_CNS_NS_DESC_LIST = 0x03,
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NVME_ID_CNS_CS_NS = 0x05,
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NVME_ID_CNS_CS_CTRL = 0x06,
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NVME_ID_CNS_NS_CS_INDEP = 0x08,
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NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
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NVME_ID_CNS_NS_PRESENT = 0x11,
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NVME_ID_CNS_CTRL_NS_LIST = 0x12,
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@ -531,6 +557,10 @@ enum {
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NVME_NS_DPS_PI_TYPE3 = 3,
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};
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enum {
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NVME_NSTAT_NRDY = 1 << 0,
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};
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enum {
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NVME_NVM_NS_16B_GUARD = 0,
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NVME_NVM_NS_32B_GUARD = 1,
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@ -1592,6 +1622,7 @@ enum {
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NVME_SC_NS_WRITE_PROTECTED = 0x20,
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NVME_SC_CMD_INTERRUPTED = 0x21,
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NVME_SC_TRANSIENT_TR_ERR = 0x22,
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NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
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NVME_SC_INVALID_IO_CMD_SET = 0x2C,
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NVME_SC_LBA_RANGE = 0x80,
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