mirror of
https://github.com/torvalds/linux
synced 2024-10-06 19:34:19 +00:00
Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue
Tony Nguyen says: ==================== Intel Wired LAN Driver Updates 2022-12-15 (igc) Muhammad Husaini Zulkifli says: This patch series fixes bugs for the Time-Sensitive Networking(TSN) Qbv Scheduling features. An overview of each patch series is given below: Patch 1: Using a first flag bit to schedule a packet to the next cycle if packet cannot fit in current Qbv cycle. Patch 2: Enable strict cycle for Qbv scheduling. Patch 3: Prevent user to set basetime less than zero during tc config. Patch 4: Allow the basetime enrollment with zero value. Patch 5: Calculate the new end time value to exclude the time interval that exceed the cycle time as user can specify the cycle time in tc config. Patch 6: Resolve the HW bugs where the gate is not fully closed. --- This contains the net patches from this original pull request: https://lore.kernel.org/netdev/20221205212414.3197525-1-anthony.l.nguyen@intel.com/ ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
8952936729
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@ -94,6 +94,8 @@ struct igc_ring {
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u8 queue_index; /* logical index of the ring*/
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u8 reg_idx; /* physical index of the ring */
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bool launchtime_enable; /* true if LaunchTime is enabled */
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ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
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ktime_t last_ff_cycle; /* Last cycle with an active first flag */
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u32 start_time;
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u32 end_time;
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@ -182,6 +184,7 @@ struct igc_adapter {
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ktime_t base_time;
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ktime_t cycle_time;
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bool qbv_enable;
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/* OS defined structs */
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struct pci_dev *pdev;
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@ -321,6 +321,8 @@
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#define IGC_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
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#define IGC_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
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#define IGC_ADVTXD_TSN_CNTX_FIRST 0x00000080
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/* Transmit Control */
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#define IGC_TCTL_EN 0x00000002 /* enable Tx */
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#define IGC_TCTL_PSP 0x00000008 /* pad short packets */
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@ -1000,25 +1000,118 @@ static int igc_write_mc_addr_list(struct net_device *netdev)
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return netdev_mc_count(netdev);
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}
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static __le32 igc_tx_launchtime(struct igc_adapter *adapter, ktime_t txtime)
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static __le32 igc_tx_launchtime(struct igc_ring *ring, ktime_t txtime,
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bool *first_flag, bool *insert_empty)
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{
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struct igc_adapter *adapter = netdev_priv(ring->netdev);
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ktime_t cycle_time = adapter->cycle_time;
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ktime_t base_time = adapter->base_time;
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ktime_t now = ktime_get_clocktai();
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ktime_t baset_est, end_of_cycle;
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u32 launchtime;
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s64 n;
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/* FIXME: when using ETF together with taprio, we may have a
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* case where 'delta' is larger than the cycle_time, this may
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* cause problems if we don't read the current value of
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* IGC_BASET, as the value writen into the launchtime
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* descriptor field may be misinterpreted.
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n = div64_s64(ktime_sub_ns(now, base_time), cycle_time);
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baset_est = ktime_add_ns(base_time, cycle_time * (n));
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end_of_cycle = ktime_add_ns(baset_est, cycle_time);
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if (ktime_compare(txtime, end_of_cycle) >= 0) {
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if (baset_est != ring->last_ff_cycle) {
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*first_flag = true;
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ring->last_ff_cycle = baset_est;
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if (ktime_compare(txtime, ring->last_tx_cycle) > 0)
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*insert_empty = true;
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}
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}
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/* Introducing a window at end of cycle on which packets
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* potentially not honor launchtime. Window of 5us chosen
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* considering software update the tail pointer and packets
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* are dma'ed to packet buffer.
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*/
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div_s64_rem(ktime_sub_ns(txtime, base_time), cycle_time, &launchtime);
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if ((ktime_sub_ns(end_of_cycle, now) < 5 * NSEC_PER_USEC))
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netdev_warn(ring->netdev, "Packet with txtime=%llu may not be honoured\n",
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txtime);
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ring->last_tx_cycle = end_of_cycle;
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launchtime = ktime_sub_ns(txtime, baset_est);
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if (launchtime > 0)
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div_s64_rem(launchtime, cycle_time, &launchtime);
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else
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launchtime = 0;
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return cpu_to_le32(launchtime);
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}
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static int igc_init_empty_frame(struct igc_ring *ring,
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struct igc_tx_buffer *buffer,
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struct sk_buff *skb)
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{
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unsigned int size;
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dma_addr_t dma;
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size = skb_headlen(skb);
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dma = dma_map_single(ring->dev, skb->data, size, DMA_TO_DEVICE);
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if (dma_mapping_error(ring->dev, dma)) {
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netdev_err_once(ring->netdev, "Failed to map DMA for TX\n");
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return -ENOMEM;
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}
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buffer->skb = skb;
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buffer->protocol = 0;
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buffer->bytecount = skb->len;
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buffer->gso_segs = 1;
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buffer->time_stamp = jiffies;
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dma_unmap_len_set(buffer, len, skb->len);
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dma_unmap_addr_set(buffer, dma, dma);
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return 0;
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}
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static int igc_init_tx_empty_descriptor(struct igc_ring *ring,
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struct sk_buff *skb,
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struct igc_tx_buffer *first)
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{
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union igc_adv_tx_desc *desc;
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u32 cmd_type, olinfo_status;
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int err;
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if (!igc_desc_unused(ring))
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return -EBUSY;
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err = igc_init_empty_frame(ring, first, skb);
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if (err)
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return err;
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cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |
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IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD |
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first->bytecount;
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olinfo_status = first->bytecount << IGC_ADVTXD_PAYLEN_SHIFT;
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desc = IGC_TX_DESC(ring, ring->next_to_use);
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desc->read.cmd_type_len = cpu_to_le32(cmd_type);
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desc->read.olinfo_status = cpu_to_le32(olinfo_status);
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desc->read.buffer_addr = cpu_to_le64(dma_unmap_addr(first, dma));
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netdev_tx_sent_queue(txring_txq(ring), skb->len);
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first->next_to_watch = desc;
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ring->next_to_use++;
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if (ring->next_to_use == ring->count)
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ring->next_to_use = 0;
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return 0;
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}
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#define IGC_EMPTY_FRAME_SIZE 60
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static void igc_tx_ctxtdesc(struct igc_ring *tx_ring,
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struct igc_tx_buffer *first,
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__le32 launch_time, bool first_flag,
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u32 vlan_macip_lens, u32 type_tucmd,
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u32 mss_l4len_idx)
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{
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if (test_bit(IGC_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
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mss_l4len_idx |= tx_ring->reg_idx << 4;
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if (first_flag)
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mss_l4len_idx |= IGC_ADVTXD_TSN_CNTX_FIRST;
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context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
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context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
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context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
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/* We assume there is always a valid Tx time available. Invalid times
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* should have been handled by the upper layers.
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*/
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if (tx_ring->launchtime_enable) {
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struct igc_adapter *adapter = netdev_priv(tx_ring->netdev);
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ktime_t txtime = first->skb->tstamp;
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skb_txtime_consumed(first->skb);
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context_desc->launch_time = igc_tx_launchtime(adapter,
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txtime);
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} else {
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context_desc->launch_time = 0;
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}
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context_desc->launch_time = launch_time;
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}
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static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first)
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static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first,
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__le32 launch_time, bool first_flag)
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{
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struct sk_buff *skb = first->skb;
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u32 vlan_macip_lens = 0;
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@ -1096,7 +1180,8 @@ static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first)
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vlan_macip_lens |= skb_network_offset(skb) << IGC_ADVTXD_MACLEN_SHIFT;
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vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;
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igc_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
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igc_tx_ctxtdesc(tx_ring, launch_time, first_flag,
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vlan_macip_lens, type_tucmd, 0);
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}
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static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
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@ -1320,6 +1405,7 @@ static int igc_tx_map(struct igc_ring *tx_ring,
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static int igc_tso(struct igc_ring *tx_ring,
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struct igc_tx_buffer *first,
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__le32 launch_time, bool first_flag,
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u8 *hdr_len)
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{
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u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
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@ -1406,8 +1492,8 @@ static int igc_tso(struct igc_ring *tx_ring,
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vlan_macip_lens |= (ip.hdr - skb->data) << IGC_ADVTXD_MACLEN_SHIFT;
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vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;
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igc_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
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type_tucmd, mss_l4len_idx);
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igc_tx_ctxtdesc(tx_ring, launch_time, first_flag,
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vlan_macip_lens, type_tucmd, mss_l4len_idx);
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return 1;
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}
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@ -1415,11 +1501,14 @@ static int igc_tso(struct igc_ring *tx_ring,
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static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb,
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struct igc_ring *tx_ring)
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{
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bool first_flag = false, insert_empty = false;
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u16 count = TXD_USE_COUNT(skb_headlen(skb));
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__be16 protocol = vlan_get_protocol(skb);
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struct igc_tx_buffer *first;
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__le32 launch_time = 0;
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u32 tx_flags = 0;
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unsigned short f;
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ktime_t txtime;
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u8 hdr_len = 0;
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int tso = 0;
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@ -1433,11 +1522,40 @@ static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb,
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count += TXD_USE_COUNT(skb_frag_size(
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&skb_shinfo(skb)->frags[f]));
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if (igc_maybe_stop_tx(tx_ring, count + 3)) {
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if (igc_maybe_stop_tx(tx_ring, count + 5)) {
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/* this is a hard error */
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return NETDEV_TX_BUSY;
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}
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if (!tx_ring->launchtime_enable)
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goto done;
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txtime = skb->tstamp;
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skb->tstamp = ktime_set(0, 0);
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launch_time = igc_tx_launchtime(tx_ring, txtime, &first_flag, &insert_empty);
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if (insert_empty) {
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struct igc_tx_buffer *empty_info;
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struct sk_buff *empty;
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void *data;
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empty_info = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
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empty = alloc_skb(IGC_EMPTY_FRAME_SIZE, GFP_ATOMIC);
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if (!empty)
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goto done;
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data = skb_put(empty, IGC_EMPTY_FRAME_SIZE);
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memset(data, 0, IGC_EMPTY_FRAME_SIZE);
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igc_tx_ctxtdesc(tx_ring, 0, false, 0, 0, 0);
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if (igc_init_tx_empty_descriptor(tx_ring,
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empty,
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empty_info) < 0)
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dev_kfree_skb_any(empty);
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}
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done:
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/* record the location of the first descriptor for this packet */
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first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
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first->type = IGC_TX_BUFFER_TYPE_SKB;
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@ -1474,11 +1592,11 @@ static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb,
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first->tx_flags = tx_flags;
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first->protocol = protocol;
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tso = igc_tso(tx_ring, first, &hdr_len);
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tso = igc_tso(tx_ring, first, launch_time, first_flag, &hdr_len);
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if (tso < 0)
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goto out_drop;
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else if (!tso)
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igc_tx_csum(tx_ring, first);
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igc_tx_csum(tx_ring, first, launch_time, first_flag);
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igc_tx_map(tx_ring, first, hdr_len);
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@ -5925,10 +6043,16 @@ static int igc_save_qbv_schedule(struct igc_adapter *adapter,
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bool queue_configured[IGC_MAX_TX_QUEUES] = { };
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u32 start_time = 0, end_time = 0;
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size_t n;
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int i;
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adapter->qbv_enable = qopt->enable;
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if (!qopt->enable)
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return igc_tsn_clear_schedule(adapter);
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if (qopt->base_time < 0)
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return -ERANGE;
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if (adapter->base_time)
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return -EALREADY;
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@ -5940,10 +6064,24 @@ static int igc_save_qbv_schedule(struct igc_adapter *adapter,
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for (n = 0; n < qopt->num_entries; n++) {
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struct tc_taprio_sched_entry *e = &qopt->entries[n];
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int i;
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end_time += e->interval;
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/* If any of the conditions below are true, we need to manually
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* control the end time of the cycle.
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* 1. Qbv users can specify a cycle time that is not equal
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* to the total GCL intervals. Hence, recalculation is
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* necessary here to exclude the time interval that
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* exceeds the cycle time.
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* 2. According to IEEE Std. 802.1Q-2018 section 8.6.9.2,
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* once the end of the list is reached, it will switch
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* to the END_OF_CYCLE state and leave the gates in the
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* same state until the next cycle is started.
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*/
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if (end_time > adapter->cycle_time ||
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n + 1 == qopt->num_entries)
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end_time = adapter->cycle_time;
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for (i = 0; i < adapter->num_tx_queues; i++) {
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struct igc_ring *ring = adapter->tx_ring[i];
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@ -5964,6 +6102,18 @@ static int igc_save_qbv_schedule(struct igc_adapter *adapter,
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start_time += e->interval;
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}
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/* Check whether a queue gets configured.
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* If not, set the start and end time to be end time.
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*/
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for (i = 0; i < adapter->num_tx_queues; i++) {
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if (!queue_configured[i]) {
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struct igc_ring *ring = adapter->tx_ring[i];
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ring->start_time = end_time;
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ring->end_time = end_time;
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}
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}
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return 0;
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}
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@ -36,7 +36,7 @@ static unsigned int igc_tsn_new_flags(struct igc_adapter *adapter)
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{
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unsigned int new_flags = adapter->flags & ~IGC_FLAG_TSN_ANY_ENABLED;
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if (adapter->base_time)
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if (adapter->qbv_enable)
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new_flags |= IGC_FLAG_TSN_QBV_ENABLED;
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if (is_any_launchtime(adapter))
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|
@ -140,15 +140,8 @@ static int igc_tsn_enable_offload(struct igc_adapter *adapter)
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wr32(IGC_STQT(i), ring->start_time);
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wr32(IGC_ENDQT(i), ring->end_time);
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if (adapter->base_time) {
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/* If we have a base_time we are in "taprio"
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* mode and we need to be strict about the
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* cycles: only transmit a packet if it can be
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* completed during that cycle.
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*/
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txqctl |= IGC_TXQCTL_STRICT_CYCLE |
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IGC_TXQCTL_STRICT_END;
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}
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txqctl |= IGC_TXQCTL_STRICT_CYCLE |
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IGC_TXQCTL_STRICT_END;
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if (ring->launchtime_enable)
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txqctl |= IGC_TXQCTL_QUEUE_MODE_LAUNCHT;
|
||||
|
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