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https://github.com/torvalds/linux
synced 2024-09-30 00:10:51 +00:00
ice: add callbacks for Embedded SYNC enablement on dpll pins
Allow the user to get and set configuration of Embedded SYNC feature on the ice driver dpll pins. Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Link: https://patch.msgid.link/20240822222513.255179-3-arkadiusz.kubalewski@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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cda1fba15c
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87abc5666a
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@ -9,6 +9,7 @@
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#define ICE_CGU_STATE_ACQ_ERR_THRESHOLD 50
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#define ICE_DPLL_PIN_IDX_INVALID 0xff
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#define ICE_DPLL_RCLK_NUM_PER_PF 1
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#define ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT 25
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/**
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* enum ice_dpll_pin_type - enumerate ice pin types:
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@ -30,6 +31,10 @@ static const char * const pin_type_name[] = {
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[ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
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};
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static const struct dpll_pin_frequency ice_esync_range[] = {
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DPLL_PIN_FREQUENCY_RANGE(0, DPLL_PIN_FREQUENCY_1_HZ),
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};
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/**
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* ice_dpll_is_reset - check if reset is in progress
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* @pf: private board structure
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@ -394,8 +399,8 @@ ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
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switch (pin_type) {
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case ICE_DPLL_PIN_TYPE_INPUT:
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ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, NULL, NULL,
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NULL, &pin->flags[0],
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ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, &pin->status,
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NULL, NULL, &pin->flags[0],
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&pin->freq, &pin->phase_adjust);
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if (ret)
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goto err;
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@ -430,7 +435,7 @@ ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
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goto err;
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parent &= ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL;
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if (ICE_AQC_SET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) {
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if (ICE_AQC_GET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) {
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pin->state[pf->dplls.eec.dpll_idx] =
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parent == pf->dplls.eec.dpll_idx ?
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DPLL_PIN_STATE_CONNECTED :
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@ -1098,6 +1103,214 @@ ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,
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return 0;
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}
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/**
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* ice_dpll_output_esync_set - callback for setting embedded sync
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* @pin: pointer to a pin
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* @pin_priv: private data pointer passed on pin registration
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* @dpll: registered dpll pointer
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* @dpll_priv: private data pointer passed on dpll registration
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* @freq: requested embedded sync frequency
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* @extack: error reporting
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*
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* Dpll subsystem callback. Handler for setting embedded sync frequency value
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* on output pin.
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*
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* Context: Acquires pf->dplls.lock
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* Return:
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* * 0 - success
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* * negative - error
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*/
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static int
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ice_dpll_output_esync_set(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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u64 freq, struct netlink_ext_ack *extack)
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{
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struct ice_dpll_pin *p = pin_priv;
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struct ice_dpll *d = dpll_priv;
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struct ice_pf *pf = d->pf;
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u8 flags = 0;
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int ret;
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if (ice_dpll_is_reset(pf, extack))
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return -EBUSY;
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mutex_lock(&pf->dplls.lock);
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if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN)
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flags = ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
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if (freq == DPLL_PIN_FREQUENCY_1_HZ) {
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if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) {
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ret = 0;
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} else {
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flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
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ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags,
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0, 0, 0);
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}
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} else {
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if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)) {
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ret = 0;
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} else {
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flags &= ~ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
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ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags,
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0, 0, 0);
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}
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}
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mutex_unlock(&pf->dplls.lock);
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return ret;
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}
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/**
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* ice_dpll_output_esync_get - callback for getting embedded sync config
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* @pin: pointer to a pin
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* @pin_priv: private data pointer passed on pin registration
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* @dpll: registered dpll pointer
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* @dpll_priv: private data pointer passed on dpll registration
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* @esync: on success holds embedded sync pin properties
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* @extack: error reporting
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*
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* Dpll subsystem callback. Handler for getting embedded sync frequency value
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* and capabilities on output pin.
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*
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* Context: Acquires pf->dplls.lock
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* Return:
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* * 0 - success
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* * negative - error
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*/
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static int
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ice_dpll_output_esync_get(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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struct dpll_pin_esync *esync,
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struct netlink_ext_ack *extack)
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{
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struct ice_dpll_pin *p = pin_priv;
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struct ice_dpll *d = dpll_priv;
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struct ice_pf *pf = d->pf;
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if (ice_dpll_is_reset(pf, extack))
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return -EBUSY;
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mutex_lock(&pf->dplls.lock);
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if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY) ||
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p->freq != DPLL_PIN_FREQUENCY_10_MHZ) {
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mutex_unlock(&pf->dplls.lock);
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return -EOPNOTSUPP;
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}
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esync->range = ice_esync_range;
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esync->range_num = ARRAY_SIZE(ice_esync_range);
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if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) {
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esync->freq = DPLL_PIN_FREQUENCY_1_HZ;
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esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT;
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} else {
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esync->freq = 0;
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esync->pulse = 0;
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}
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mutex_unlock(&pf->dplls.lock);
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return 0;
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}
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/**
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* ice_dpll_input_esync_set - callback for setting embedded sync
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* @pin: pointer to a pin
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* @pin_priv: private data pointer passed on pin registration
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* @dpll: registered dpll pointer
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* @dpll_priv: private data pointer passed on dpll registration
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* @freq: requested embedded sync frequency
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* @extack: error reporting
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*
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* Dpll subsystem callback. Handler for setting embedded sync frequency value
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* on input pin.
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*
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* Context: Acquires pf->dplls.lock
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* Return:
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* * 0 - success
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* * negative - error
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*/
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static int
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ice_dpll_input_esync_set(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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u64 freq, struct netlink_ext_ack *extack)
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{
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struct ice_dpll_pin *p = pin_priv;
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struct ice_dpll *d = dpll_priv;
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struct ice_pf *pf = d->pf;
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u8 flags_en = 0;
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int ret;
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if (ice_dpll_is_reset(pf, extack))
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return -EBUSY;
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mutex_lock(&pf->dplls.lock);
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if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN)
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flags_en = ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
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if (freq == DPLL_PIN_FREQUENCY_1_HZ) {
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if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) {
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ret = 0;
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} else {
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flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
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ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0,
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flags_en, 0, 0);
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}
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} else {
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if (!(p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)) {
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ret = 0;
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} else {
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flags_en &= ~ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
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ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0,
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flags_en, 0, 0);
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}
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}
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mutex_unlock(&pf->dplls.lock);
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return ret;
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}
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/**
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* ice_dpll_input_esync_get - callback for getting embedded sync config
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* @pin: pointer to a pin
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* @pin_priv: private data pointer passed on pin registration
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* @dpll: registered dpll pointer
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* @dpll_priv: private data pointer passed on dpll registration
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* @esync: on success holds embedded sync pin properties
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* @extack: error reporting
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*
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* Dpll subsystem callback. Handler for getting embedded sync frequency value
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* and capabilities on input pin.
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*
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* Context: Acquires pf->dplls.lock
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* Return:
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* * 0 - success
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* * negative - error
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*/
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static int
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ice_dpll_input_esync_get(const struct dpll_pin *pin, void *pin_priv,
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const struct dpll_device *dpll, void *dpll_priv,
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struct dpll_pin_esync *esync,
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struct netlink_ext_ack *extack)
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{
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struct ice_dpll_pin *p = pin_priv;
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struct ice_dpll *d = dpll_priv;
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struct ice_pf *pf = d->pf;
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if (ice_dpll_is_reset(pf, extack))
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return -EBUSY;
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mutex_lock(&pf->dplls.lock);
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if (!(p->status & ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP) ||
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p->freq != DPLL_PIN_FREQUENCY_10_MHZ) {
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mutex_unlock(&pf->dplls.lock);
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return -EOPNOTSUPP;
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}
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esync->range = ice_esync_range;
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esync->range_num = ARRAY_SIZE(ice_esync_range);
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if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) {
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esync->freq = DPLL_PIN_FREQUENCY_1_HZ;
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esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT;
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} else {
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esync->freq = 0;
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esync->pulse = 0;
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}
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mutex_unlock(&pf->dplls.lock);
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return 0;
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}
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/**
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* ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
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* @pin: pointer to a pin
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@ -1222,6 +1435,8 @@ static const struct dpll_pin_ops ice_dpll_input_ops = {
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.phase_adjust_get = ice_dpll_pin_phase_adjust_get,
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.phase_adjust_set = ice_dpll_input_phase_adjust_set,
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.phase_offset_get = ice_dpll_phase_offset_get,
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.esync_set = ice_dpll_input_esync_set,
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.esync_get = ice_dpll_input_esync_get,
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};
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static const struct dpll_pin_ops ice_dpll_output_ops = {
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@ -1232,6 +1447,8 @@ static const struct dpll_pin_ops ice_dpll_output_ops = {
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.direction_get = ice_dpll_output_direction,
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.phase_adjust_get = ice_dpll_pin_phase_adjust_get,
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.phase_adjust_set = ice_dpll_output_phase_adjust_set,
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.esync_set = ice_dpll_output_esync_set,
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.esync_get = ice_dpll_output_esync_get,
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};
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static const struct dpll_device_ops ice_dpll_ops = {
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@ -31,6 +31,7 @@ struct ice_dpll_pin {
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struct dpll_pin_properties prop;
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u32 freq;
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s32 phase_adjust;
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u8 status;
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};
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/** ice_dpll - store info required for DPLL control
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