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https://github.com/torvalds/linux
synced 2024-07-23 03:29:48 +00:00
powerpc/sysdev: drop simple gpio
There is a config item CONFIG_SIMPLE_GPIO which provides simple memory mapped GPIOs specific to powerpc. However, the only platform which selects this option is mpc5200, and this platform doesn't use it. There are three boards calling simple_gpiochip_init(), but as they don't select CONFIG_SIMPLE_GPIO, this is just a nop. Simple_gpio is just redundant with the generic MMIO GPIO driver which can be found in driver/gpio/ and selected via CONFIG_GPIO_GENERIC_PLATFORM, so drop simple_gpio driver. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/bf930402613b41b42d0441b784e0cc43fc18d1fb.1572529632.git.christophe.leroy@c-s.fr
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
6b7c095a51
commit
8795a739e5
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@ -47,36 +47,6 @@ Example (LS2080A-RDB):
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reg = <0x3 0 0x10000>;
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};
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* Freescale BCSR GPIO banks
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Some BCSR registers act as simple GPIO controllers, each such
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register can be represented by the gpio-controller node.
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Required properities:
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- compatible : Should be "fsl,<board>-bcsr-gpio".
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- reg : Should contain the address and the length of the GPIO bank
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register.
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters (currently unused).
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- gpio-controller : Marks the port as GPIO controller.
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Example:
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bcsr@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8360mds-bcsr";
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reg = <1 0 0x8000>;
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ranges = <0 1 0 0x8000>;
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bcsr13: gpio-controller@d {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8360mds-bcsr-gpio";
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reg = <0xd 1>;
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gpio-controller;
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};
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};
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* Freescale on-board FPGA connected on I2C bus
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Some Freescale boards like BSC9132QDS have on board FPGA connected on
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@ -15,7 +15,6 @@ CONFIG_PPC_MEDIA5200=y
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CONFIG_PPC_MPC5200_BUGFIX=y
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CONFIG_PPC_MPC5200_LPBFIFO=m
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# CONFIG_PPC_PMAC is not set
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CONFIG_SIMPLE_GPIO=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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@ -39,7 +39,6 @@
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/simple_gpio.h>
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#include <soc/fsl/qe/qe.h>
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#include <soc/fsl/qe/qe_ic.h>
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@ -181,12 +180,6 @@ static int __init mpc836x_usb_cfg(void)
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qe_usb_clock_set(QE_CLK21, 48000000);
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} else {
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setbits8(&bcsr[13], BCSR13_USBMODE);
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/*
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* The BCSR GPIOs are used to control power and
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* speed of the USB transceiver. This is needed for
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* the USB Host only.
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*/
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simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
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}
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of_node_put(np);
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@ -43,7 +43,6 @@
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/simple_gpio.h>
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#include <soc/fsl/qe/qe.h>
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#include <soc/fsl/qe/qe_ic.h>
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#include <asm/mpic.h>
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@ -350,11 +349,6 @@ machine_arch_initcall(mpc8569_mds, board_fixups);
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static int __init mpc85xx_publish_devices(void)
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{
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if (machine_is(mpc8568_mds))
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simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
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if (machine_is(mpc8569_mds))
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simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
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return mpc85xx_common_publish_devices();
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}
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@ -34,7 +34,6 @@
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#include <linux/of_platform.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/simple_gpio.h>
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#include "mpc86xx.h"
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@ -93,9 +92,6 @@ static const struct of_device_id mpc8610_ids[] __initconst = {
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static int __init mpc8610_declare_of_platform_devices(void)
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{
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/* Firstly, register PIXIS GPIOs. */
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simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
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/* Enable wakeup on PIXIS' event IRQ. */
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mpc8610_suspend_init();
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@ -303,16 +303,6 @@ config GEN_RTC
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replacing their get_rtc_time/set_rtc_time callbacks with
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a proper RTC device driver.
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config SIMPLE_GPIO
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bool "Support for simple, memory-mapped GPIO controllers"
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depends on PPC
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select GPIOLIB
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help
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Say Y here to support simple, memory-mapped GPIO controllers.
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These are usually BCSRs used to control board's switches, LEDs,
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chip-selects, Ethernet/USB PHY's power and various other small
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on-board peripherals.
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config MCU_MPC8349EMITX
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bool "MPC8349E-mITX MCU driver"
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depends on I2C=y && PPC_83xx
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@ -24,7 +24,6 @@ obj-$(CONFIG_FSL_CORENET_RCPM) += fsl_rcpm.o
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obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
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obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
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obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
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obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
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obj-$(CONFIG_FSL_RIO) += fsl_rio.o fsl_rmu.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
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@ -1,143 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Simple Memory-Mapped GPIOs
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*
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* Copyright (c) MontaVista Software, Inc. 2008.
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*
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/gpio/driver.h>
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#include <linux/slab.h>
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#include <asm/prom.h>
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#include "simple_gpio.h"
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struct u8_gpio_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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/* shadowed data register to clear/set bits safely */
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u8 data;
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};
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static u8 u8_pin2mask(unsigned int pin)
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{
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return 1 << (8 - 1 - pin);
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}
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static int u8_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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return !!(in_8(mm_gc->regs) & u8_pin2mask(gpio));
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}
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static void u8_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct u8_gpio_chip *u8_gc = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&u8_gc->lock, flags);
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if (val)
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u8_gc->data |= u8_pin2mask(gpio);
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else
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u8_gc->data &= ~u8_pin2mask(gpio);
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out_8(mm_gc->regs, u8_gc->data);
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spin_unlock_irqrestore(&u8_gc->lock, flags);
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}
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static int u8_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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return 0;
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}
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static int u8_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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u8_gpio_set(gc, gpio, val);
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return 0;
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}
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static void u8_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
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{
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struct u8_gpio_chip *u8_gc =
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container_of(mm_gc, struct u8_gpio_chip, mm_gc);
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u8_gc->data = in_8(mm_gc->regs);
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}
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static int __init u8_simple_gpiochip_add(struct device_node *np)
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{
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int ret;
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struct u8_gpio_chip *u8_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct gpio_chip *gc;
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u8_gc = kzalloc(sizeof(*u8_gc), GFP_KERNEL);
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if (!u8_gc)
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return -ENOMEM;
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spin_lock_init(&u8_gc->lock);
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mm_gc = &u8_gc->mm_gc;
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gc = &mm_gc->gc;
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mm_gc->save_regs = u8_gpio_save_regs;
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gc->ngpio = 8;
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gc->direction_input = u8_gpio_dir_in;
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gc->direction_output = u8_gpio_dir_out;
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gc->get = u8_gpio_get;
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gc->set = u8_gpio_set;
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ret = of_mm_gpiochip_add_data(np, mm_gc, u8_gc);
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if (ret)
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goto err;
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return 0;
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err:
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kfree(u8_gc);
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return ret;
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}
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void __init simple_gpiochip_init(const char *compatible)
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{
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struct device_node *np;
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for_each_compatible_node(np, NULL, compatible) {
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int ret;
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struct resource r;
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ret = of_address_to_resource(np, 0, &r);
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if (ret)
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goto err;
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switch (resource_size(&r)) {
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case 1:
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ret = u8_simple_gpiochip_add(np);
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if (ret)
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goto err;
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break;
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default:
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/*
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* Whenever you need support for GPIO bank width > 1,
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* please just turn u8_ code into huge macros, and
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* construct needed uX_ code with it.
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*/
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ret = -ENOSYS;
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goto err;
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}
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continue;
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err:
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pr_err("%pOF: registration failed, status %d\n", np, ret);
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}
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}
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@ -1,13 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SYSDEV_SIMPLE_GPIO_H
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#define __SYSDEV_SIMPLE_GPIO_H
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#include <linux/errno.h>
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#ifdef CONFIG_SIMPLE_GPIO
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extern void simple_gpiochip_init(const char *compatible);
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#else
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static inline void simple_gpiochip_init(const char *compatible) {}
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#endif /* CONFIG_SIMPLE_GPIO */
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#endif /* __SYSDEV_SIMPLE_GPIO_H */
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