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synced 2024-10-22 03:09:41 +00:00
spi: stm32-qspi: add automatic poll status feature
STM32 QSPI is able to automatically poll a specified register inside the memory and relieve the CPU from this task. As example, when erasing a large memory area, we got cpu load equal to 50%. This patch allows to perform the same operation with a cpu load around 2%. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210518162754.15940-4-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -36,6 +36,7 @@
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#define CR_FTIE BIT(18)
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#define CR_FTIE BIT(18)
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#define CR_SMIE BIT(19)
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#define CR_SMIE BIT(19)
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#define CR_TOIE BIT(20)
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#define CR_TOIE BIT(20)
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#define CR_APMS BIT(22)
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#define CR_PRESC_MASK GENMASK(31, 24)
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#define CR_PRESC_MASK GENMASK(31, 24)
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#define QSPI_DCR 0x04
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#define QSPI_DCR 0x04
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@ -53,6 +54,7 @@
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#define QSPI_FCR 0x0c
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#define QSPI_FCR 0x0c
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#define FCR_CTEF BIT(0)
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#define FCR_CTEF BIT(0)
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#define FCR_CTCF BIT(1)
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#define FCR_CTCF BIT(1)
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#define FCR_CSMF BIT(3)
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#define QSPI_DLR 0x10
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#define QSPI_DLR 0x10
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@ -107,6 +109,7 @@ struct stm32_qspi {
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u32 clk_rate;
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u32 clk_rate;
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struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
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struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
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struct completion data_completion;
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struct completion data_completion;
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struct completion match_completion;
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u32 fmode;
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u32 fmode;
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struct dma_chan *dma_chtx;
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struct dma_chan *dma_chtx;
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@ -115,6 +118,7 @@ struct stm32_qspi {
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u32 cr_reg;
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u32 cr_reg;
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u32 dcr_reg;
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u32 dcr_reg;
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unsigned long status_timeout;
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/*
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/*
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* to protect device configuration, could be different between
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* to protect device configuration, could be different between
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@ -128,11 +132,20 @@ static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
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struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
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struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
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u32 cr, sr;
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u32 cr, sr;
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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sr = readl_relaxed(qspi->io_base + QSPI_SR);
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sr = readl_relaxed(qspi->io_base + QSPI_SR);
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if (cr & CR_SMIE && sr & SR_SMF) {
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/* disable irq */
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cr &= ~CR_SMIE;
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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complete(&qspi->match_completion);
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return IRQ_HANDLED;
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}
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if (sr & (SR_TEF | SR_TCF)) {
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if (sr & (SR_TEF | SR_TCF)) {
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/* disable irq */
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/* disable irq */
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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cr &= ~CR_TCIE & ~CR_TEIE;
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cr &= ~CR_TCIE & ~CR_TEIE;
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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complete(&qspi->data_completion);
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complete(&qspi->data_completion);
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@ -319,6 +332,24 @@ static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
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return err;
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return err;
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}
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}
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static int stm32_qspi_wait_poll_status(struct stm32_qspi *qspi,
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const struct spi_mem_op *op)
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{
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u32 cr;
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reinit_completion(&qspi->match_completion);
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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writel_relaxed(cr | CR_SMIE, qspi->io_base + QSPI_CR);
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if (!wait_for_completion_timeout(&qspi->match_completion,
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msecs_to_jiffies(qspi->status_timeout)))
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return -ETIMEDOUT;
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writel_relaxed(FCR_CSMF, qspi->io_base + QSPI_FCR);
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return 0;
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}
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static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
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static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
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{
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{
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if (buswidth == 4)
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if (buswidth == 4)
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@ -332,7 +363,7 @@ static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
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struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
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struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
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struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
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struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
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u32 ccr, cr;
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u32 ccr, cr;
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int timeout, err = 0;
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int timeout, err = 0, err_poll_status = 0;
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dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
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dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
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op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
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op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
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@ -378,6 +409,9 @@ static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
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if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
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if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
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writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
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writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
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if (qspi->fmode == CCR_FMODE_APM)
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err_poll_status = stm32_qspi_wait_poll_status(qspi, op);
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err = stm32_qspi_tx(qspi, op);
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err = stm32_qspi_tx(qspi, op);
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/*
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/*
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@ -387,7 +421,7 @@ static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
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* byte of device (device size - fifo size). like device size is not
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* byte of device (device size - fifo size). like device size is not
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* knows, the prefetching is always stop.
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* knows, the prefetching is always stop.
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*/
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*/
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if (err || qspi->fmode == CCR_FMODE_MM)
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if (err || err_poll_status || qspi->fmode == CCR_FMODE_MM)
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goto abort;
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goto abort;
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/* wait end of tx in indirect mode */
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/* wait end of tx in indirect mode */
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@ -406,15 +440,49 @@ static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
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cr, !(cr & CR_ABORT), 1,
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cr, !(cr & CR_ABORT), 1,
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STM32_ABT_TIMEOUT_US);
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STM32_ABT_TIMEOUT_US);
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writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
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writel_relaxed(FCR_CTCF | FCR_CSMF, qspi->io_base + QSPI_FCR);
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if (err || timeout)
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if (err || err_poll_status || timeout)
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dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
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dev_err(qspi->dev, "%s err:%d err_poll_status:%d abort timeout:%d\n",
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__func__, err, timeout);
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__func__, err, err_poll_status, timeout);
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return err;
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return err;
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}
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}
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static int stm32_qspi_poll_status(struct spi_mem *mem, const struct spi_mem_op *op,
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u16 mask, u16 match,
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unsigned long initial_delay_us,
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unsigned long polling_rate_us,
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unsigned long timeout_ms)
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{
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struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
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int ret;
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if (!spi_mem_supports_op(mem, op))
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return -EOPNOTSUPP;
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ret = pm_runtime_get_sync(qspi->dev);
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if (ret < 0) {
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pm_runtime_put_noidle(qspi->dev);
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return ret;
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}
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mutex_lock(&qspi->lock);
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writel_relaxed(mask, qspi->io_base + QSPI_PSMKR);
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writel_relaxed(match, qspi->io_base + QSPI_PSMAR);
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qspi->fmode = CCR_FMODE_APM;
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qspi->status_timeout = timeout_ms;
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ret = stm32_qspi_send(mem, op);
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mutex_unlock(&qspi->lock);
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pm_runtime_mark_last_busy(qspi->dev);
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pm_runtime_put_autosuspend(qspi->dev);
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return ret;
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}
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static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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{
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struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
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struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
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@ -527,7 +595,7 @@ static int stm32_qspi_setup(struct spi_device *spi)
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flash->presc = presc;
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flash->presc = presc;
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mutex_lock(&qspi->lock);
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mutex_lock(&qspi->lock);
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qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
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qspi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
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writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
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writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
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/* set dcr fsize to max address */
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/* set dcr fsize to max address */
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.exec_op = stm32_qspi_exec_op,
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.exec_op = stm32_qspi_exec_op,
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.dirmap_create = stm32_qspi_dirmap_create,
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.dirmap_create = stm32_qspi_dirmap_create,
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.dirmap_read = stm32_qspi_dirmap_read,
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.dirmap_read = stm32_qspi_dirmap_read,
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.poll_status = stm32_qspi_poll_status,
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};
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};
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static int stm32_qspi_probe(struct platform_device *pdev)
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static int stm32_qspi_probe(struct platform_device *pdev)
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}
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}
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init_completion(&qspi->data_completion);
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init_completion(&qspi->data_completion);
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init_completion(&qspi->match_completion);
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qspi->clk = devm_clk_get(dev, NULL);
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qspi->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(qspi->clk)) {
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if (IS_ERR(qspi->clk)) {
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