mirror of
https://github.com/torvalds/linux
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ARMv8 Juno/fast models updates for v5.1
1. Support for Fixed Virtual Platforms(FVP) Base RevC model to enable
development of software around the new features available
2. Addition of dynamic-power-coefficient information for CPUs on Juno
3. Miscellaneous changes like re-ordering device nodes, using existing
macros for GIC flags in interrupt-maps and using list instead of
tuple(which is wrong but works as number of interrupt cells is 1)
for mmci interrupts
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Merge tag 'juno-updates-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
ARMv8 Juno/fast models updates for v5.1
1. Support for Fixed Virtual Platforms(FVP) Base RevC model to enable
development of software around the new features available
2. Addition of dynamic-power-coefficient information for CPUs on Juno
3. Miscellaneous changes like re-ordering device nodes, using existing
macros for GIC flags in interrupt-maps and using list instead of
tuple(which is wrong but works as number of interrupt cells is 1)
for mmci interrupts
* tag 'juno-updates-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Add cpu dynamic-power-coefficient information
arm64: dts: fast models: Add DTS fo Base RevC FVP
arm64: dts: juno/fast models: sort couple of device nodes
arm64: dts: models: use list instead of tuple for mmci interrupts
arm64: dts: juno/fast models: using GIC macros instead of hardcoded values
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
839c291de9
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@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \
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dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
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|
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@ -14,6 +14,6 @@ gic: interrupt-controller@2c001000 {
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<0x0 0x2c002000 0 0x2000>,
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<0x0 0x2c004000 0 0x2000>,
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<0x0 0x2c006000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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};
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@ -17,7 +17,7 @@ gic: interrupt-controller@2f000000 {
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<0x0 0x2c000000 0x0 0x2000>,
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<0x0 0x2c010000 0x0 0x2000>,
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<0x0 0x2c02f000 0x0 0x2000>;
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interrupts = <1 9 4>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its: its@2f020000 {
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compatible = "arm,gic-v3-its";
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@ -7,6 +7,8 @@
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/memreserve/ 0x80000000 0x00010000;
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/ {
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@ -67,26 +69,26 @@ memory@80000000 {
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <100000000>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 60 4>,
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<0 61 4>,
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<0 62 4>,
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<0 63 4>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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};
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watchdog@2a440000 {
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compatible = "arm,sbsa-gwdt";
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reg = <0x0 0x2a440000 0 0x1000>,
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<0x0 0x2a450000 0 0x1000>;
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interrupts = <0 27 4>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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timeout-sec = <30>;
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};
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@ -105,49 +107,49 @@ smb@8000000 {
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
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<0 0 1 &gic 0 0 0 1 4>,
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<0 0 2 &gic 0 0 0 2 4>,
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<0 0 3 &gic 0 0 0 3 4>,
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<0 0 4 &gic 0 0 0 4 4>,
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<0 0 5 &gic 0 0 0 5 4>,
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<0 0 6 &gic 0 0 0 6 4>,
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<0 0 7 &gic 0 0 0 7 4>,
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<0 0 8 &gic 0 0 0 8 4>,
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<0 0 9 &gic 0 0 0 9 4>,
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<0 0 10 &gic 0 0 0 10 4>,
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<0 0 11 &gic 0 0 0 11 4>,
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<0 0 12 &gic 0 0 0 12 4>,
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<0 0 13 &gic 0 0 0 13 4>,
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<0 0 14 &gic 0 0 0 14 4>,
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<0 0 15 &gic 0 0 0 15 4>,
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<0 0 16 &gic 0 0 0 16 4>,
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<0 0 17 &gic 0 0 0 17 4>,
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<0 0 18 &gic 0 0 0 18 4>,
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<0 0 19 &gic 0 0 0 19 4>,
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<0 0 20 &gic 0 0 0 20 4>,
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<0 0 21 &gic 0 0 0 21 4>,
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<0 0 22 &gic 0 0 0 22 4>,
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<0 0 23 &gic 0 0 0 23 4>,
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<0 0 24 &gic 0 0 0 24 4>,
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<0 0 25 &gic 0 0 0 25 4>,
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<0 0 26 &gic 0 0 0 26 4>,
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<0 0 27 &gic 0 0 0 27 4>,
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<0 0 28 &gic 0 0 0 28 4>,
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<0 0 29 &gic 0 0 0 29 4>,
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<0 0 30 &gic 0 0 0 30 4>,
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<0 0 31 &gic 0 0 0 31 4>,
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<0 0 32 &gic 0 0 0 32 4>,
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<0 0 33 &gic 0 0 0 33 4>,
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<0 0 34 &gic 0 0 0 34 4>,
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<0 0 35 &gic 0 0 0 35 4>,
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<0 0 36 &gic 0 0 0 36 4>,
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<0 0 37 &gic 0 0 0 37 4>,
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<0 0 38 &gic 0 0 0 38 4>,
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<0 0 39 &gic 0 0 0 39 4>,
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<0 0 40 &gic 0 0 0 40 4>,
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<0 0 41 &gic 0 0 0 41 4>,
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<0 0 42 &gic 0 0 0 42 4>;
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interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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ethernet@2,02000000 {
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compatible = "smsc,lan91c111";
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277
arch/arm64/boot/dts/arm/fvp-base-revc.dts
Normal file
277
arch/arm64/boot/dts/arm/fvp-base-revc.dts
Normal file
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@ -0,0 +1,277 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd. Fast Models
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*
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* Architecture Envelope Model (AEM) ARMv8-A
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* ARMAEMv8AMPCT
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*
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* FVP Base RevC
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/memreserve/ 0x80000000 0x00010000;
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#include "rtsm_ve-motherboard.dtsi"
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#include "rtsm_ve-motherboard-rs2.dtsi"
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/ {
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model = "FVP Base RevC";
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compatible = "arm,fvp-base-revc", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x000>;
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enable-method = "psci";
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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};
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cpu4: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x10000>;
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enable-method = "psci";
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};
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cpu5: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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||||
reg = <0x0 0x10100>;
|
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enable-method = "psci";
|
||||
};
|
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cpu6: cpu@10200 {
|
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device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x10200>;
|
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enable-method = "psci";
|
||||
};
|
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cpu7: cpu@10300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,armv8";
|
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reg = <0x0 0x10300>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
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device_type = "memory";
|
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reg = <0x00000000 0x80000000 0 0x80000000>,
|
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<0x00000008 0x80000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* Chipselect 2,00000000 is physically at 0x18000000 */
|
||||
vram: vram@18000000 {
|
||||
/* 8 MB of designated video RAM */
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00000000 0x18000000 0 0x00800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2f000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x2f000000 0 0x10000>, // GICD
|
||||
<0x0 0x2f100000 0 0x200000>, // GICR
|
||||
<0x0 0x2c000000 0 0x2000>, // GICC
|
||||
<0x0 0x2c010000 0 0x2000>, // GICH
|
||||
<0x0 0x2c02f000 0 0x2000>; // GICV
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
its: its@2f020000 {
|
||||
#msi-cells = <1>;
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
|
||||
msi-controller;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spe-pmu {
|
||||
compatible = "arm,statistical-profiling-extension-v1";
|
||||
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci: pci@40000000 {
|
||||
#address-cells = <0x3>;
|
||||
#size-cells = <0x2>;
|
||||
#interrupt-cells = <0x1>;
|
||||
compatible = "pci-host-ecam-generic";
|
||||
device_type = "pci";
|
||||
bus-range = <0x0 0x1>;
|
||||
reg = <0x0 0x40000000 0x0 0x10000000>;
|
||||
ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
|
||||
interrupt-map = <0 0 0 1 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &gic GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &gic GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
msi-map = <0x0 &its 0x0 0x10000>;
|
||||
iommu-map = <0x0 &smmu 0x0 0x10000>;
|
||||
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
smmu: smmu@2b400000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
reg = <0x0 0x2b400000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
|
||||
dma-coherent;
|
||||
#iommu-cells = <1>;
|
||||
msi-parent = <&its 0x10000>;
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "arm,rtsm-display", "panel-dpi";
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&clcd_pads>;
|
||||
};
|
||||
};
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <63500127>;
|
||||
hactive = <1024>;
|
||||
hback-porch = <152>;
|
||||
hfront-porch = <48>;
|
||||
hsync-len = <104>;
|
||||
vactive = <768>;
|
||||
vback-porch = <23>;
|
||||
vfront-porch = <3>;
|
||||
vsync-len = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
smb@8000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
motherboard {
|
||||
iofpga@3,00000000 {
|
||||
clcd@1f0000 {
|
||||
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -18,7 +18,7 @@ memtimer: timer@2a810000 {
|
|||
status = "disabled";
|
||||
frame@2a830000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <0 60 4>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -220,6 +220,41 @@ stm_out_port: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
replicator@20120000 {
|
||||
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
||||
reg = <0 0x20120000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* replicator output ports */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_out_port0: endpoint {
|
||||
remote-endpoint = <&tpiu_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator_out_port1: endpoint {
|
||||
remote-endpoint = <&etr_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
in-ports {
|
||||
port {
|
||||
replicator_in_port0: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_debug0: cpu-debug@22010000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x22010000 0x0 0x1000>;
|
||||
|
|
@ -452,41 +487,6 @@ cluster1_etm3_out_port: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
replicator@20120000 {
|
||||
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
||||
reg = <0 0x20120000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* replicator output ports */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_out_port0: endpoint {
|
||||
remote-endpoint = <&tpiu_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator_out_port1: endpoint {
|
||||
remote-endpoint = <&etr_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
in-ports {
|
||||
port {
|
||||
replicator_in_port0: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sram: sram@2e000000 {
|
||||
compatible = "arm,juno-sram-ns", "mmio-sram";
|
||||
reg = <0x0 0x2e000000 0x0 0x8000>;
|
||||
|
|
@ -520,10 +520,10 @@ pcie_ctlr: pcie@40000000 {
|
|||
<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
|
||||
<0 0 0 2 &gic 0 0 0 137 4>,
|
||||
<0 0 0 3 &gic 0 0 0 138 4>,
|
||||
<0 0 0 4 &gic 0 0 0 139 4>;
|
||||
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
msi-parent = <&v2m_0>;
|
||||
status = "disabled";
|
||||
iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
|
||||
|
|
@ -787,19 +787,19 @@ smb@8000000 {
|
|||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 15>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
site2: tlx@60000000 {
|
||||
|
|
@ -809,6 +809,6 @@ site2: tlx@60000000 {
|
|||
ranges = <0 0 0x60000000 0x10000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0>;
|
||||
interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -99,6 +99,7 @@ A72_0: cpu@0 {
|
|||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <450>;
|
||||
};
|
||||
|
||||
A72_1: cpu@1 {
|
||||
|
|
@ -116,6 +117,7 @@ A72_1: cpu@1 {
|
|||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <450>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
|
|
@ -133,6 +135,7 @@ A53_0: cpu@100 {
|
|||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
|
|
@ -150,6 +153,7 @@ A53_1: cpu@101 {
|
|||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
|
|
@ -167,6 +171,7 @@ A53_2: cpu@102 {
|
|||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
|
|
@ -184,6 +189,7 @@ A53_3: cpu@103 {
|
|||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A72_L2: l2-cache0 {
|
||||
|
|
|
|||
|
|
@ -98,6 +98,7 @@ A57_0: cpu@0 {
|
|||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <530>;
|
||||
};
|
||||
|
||||
A57_1: cpu@1 {
|
||||
|
|
@ -115,6 +116,7 @@ A57_1: cpu@1 {
|
|||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <530>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
|
|
@ -132,6 +134,7 @@ A53_0: cpu@100 {
|
|||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
|
|
@ -149,6 +152,7 @@ A53_1: cpu@101 {
|
|||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
|
|
@ -166,6 +170,7 @@ A53_2: cpu@102 {
|
|||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
|
|
@ -183,6 +188,7 @@ A53_3: cpu@103 {
|
|||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <578>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A57_L2: l2-cache0 {
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/memreserve/ 0x80000000 0x00010000;
|
||||
|
||||
#include "rtsm_ve-motherboard.dtsi"
|
||||
|
|
@ -101,24 +103,24 @@ gic: interrupt-controller@2c001000 {
|
|||
<0x0 0x2c002000 0 0x2000>,
|
||||
<0x0 0x2c004000 0 0x2000>,
|
||||
<0x0 0x2c006000 0 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 60 4>,
|
||||
<0 61 4>,
|
||||
<0 62 4>,
|
||||
<0 63 4>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
panel {
|
||||
|
|
@ -144,48 +146,48 @@ smb@8000000 {
|
|||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
27
arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
Normal file
27
arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* ARM Ltd. Fast Models
|
||||
*
|
||||
* "rs2" extension for the v2m motherboard
|
||||
*/
|
||||
/ {
|
||||
smb@8000000 {
|
||||
motherboard {
|
||||
arm,v2m-memory-map = "rs2";
|
||||
|
||||
iofpga@3,00000000 {
|
||||
virtio-p9@140000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x140000 0x200>;
|
||||
interrupts = <43>;
|
||||
};
|
||||
|
||||
virtio-net@150000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x150000 0x200>;
|
||||
interrupts = <44>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -86,7 +86,7 @@ aaci@40000 {
|
|||
mmci@50000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x050000 0x1000>;
|
||||
interrupts = <9 10>;
|
||||
interrupts = <9>, <10>;
|
||||
cd-gpios = <&v2m_sysreg 0 0>;
|
||||
wp-gpios = <&v2m_sysreg 1 0>;
|
||||
max-frequency = <12000000>;
|
||||
|
|
@ -167,6 +167,12 @@ v2m_timer23: timer@120000 {
|
|||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
virtio-block@130000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x130000 0x200>;
|
||||
interrupts = <42>;
|
||||
};
|
||||
|
||||
rtc@170000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x170000 0x1000>;
|
||||
|
|
@ -193,12 +199,6 @@ clcd_pads: endpoint {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
virtio-block@130000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x130000 0x200>;
|
||||
interrupts = <42>;
|
||||
};
|
||||
};
|
||||
|
||||
v2m_fixed_3v3: v2m-3v3 {
|
||||
|
|
|
|||
Loading…
Reference in a new issue