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MIPS: Allow RIXI to be used on non-R2 or R6 cores
Some processors, like Broadcom's BMIPS4380 and BMIPS5000 support RIXI and the "rotr" instruction, which can be used to get a slightly more efficient page table layout. Introduce a CONFIG_CPU_HAS_RIXI such that those cores can benefit from this feature. Perform the conditional check updates where relevant. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: pgynther@google.com Cc: paul.burton@imgtec.com Cc: ddaney.cavm@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12505/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -1996,11 +1996,13 @@ config CPU_MIPSR1
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config CPU_MIPSR2
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config CPU_MIPSR2
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bool
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bool
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default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
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default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
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select CPU_HAS_RIXI
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select MIPS_SPRAM
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select MIPS_SPRAM
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config CPU_MIPSR6
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config CPU_MIPSR6
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bool
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bool
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default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
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default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
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select CPU_HAS_RIXI
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select HAVE_ARCH_BITREVERSE
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select HAVE_ARCH_BITREVERSE
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select MIPS_ASID_BITS_VARIABLE
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select MIPS_ASID_BITS_VARIABLE
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select MIPS_SPRAM
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select MIPS_SPRAM
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@ -2421,6 +2423,9 @@ config CPU_HAS_WB
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config XKS01
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config XKS01
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bool
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bool
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config CPU_HAS_RIXI
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bool
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#
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#
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# Vectored interrupt mode is an R2 feature
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# Vectored interrupt mode is an R2 feature
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#
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#
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@ -104,7 +104,7 @@ enum pgtable_bits {
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enum pgtable_bits {
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enum pgtable_bits {
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/* Used only by software (masked out before writing EntryLo*) */
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/* Used only by software (masked out before writing EntryLo*) */
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_PAGE_PRESENT_SHIFT,
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_PAGE_PRESENT_SHIFT,
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#if !defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_MIPSR6)
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#if !defined(CONFIG_CPU_HAS_RIXI)
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_PAGE_NO_READ_SHIFT,
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_PAGE_NO_READ_SHIFT,
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#endif
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#endif
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_PAGE_WRITE_SHIFT,
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_PAGE_WRITE_SHIFT,
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@ -115,7 +115,7 @@ enum pgtable_bits {
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#endif
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#endif
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/* Used by TLB hardware (placed in EntryLo*) */
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/* Used by TLB hardware (placed in EntryLo*) */
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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#if defined(CONFIG_CPU_HAS_RIXI)
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_PAGE_NO_EXEC_SHIFT,
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_PAGE_NO_EXEC_SHIFT,
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_PAGE_NO_READ_SHIFT,
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_PAGE_NO_READ_SHIFT,
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#endif
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#endif
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@ -139,7 +139,7 @@ enum pgtable_bits {
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/* Used by TLB hardware (placed in EntryLo*) */
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/* Used by TLB hardware (placed in EntryLo*) */
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#if defined(CONFIG_XPA)
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#if defined(CONFIG_XPA)
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# define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
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# define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
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#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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#elif defined(CONFIG_CPU_HAS_RIXI)
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# define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
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# define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
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#endif
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#endif
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#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
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#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
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@ -180,7 +180,7 @@ enum pgtable_bits {
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*/
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*/
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static inline uint64_t pte_to_entrylo(unsigned long pte_val)
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static inline uint64_t pte_to_entrylo(unsigned long pte_val)
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{
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{
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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#ifdef CONFIG_CPU_HAS_RIXI
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if (cpu_has_rixi) {
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if (cpu_has_rixi) {
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int sa;
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int sa;
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#ifdef CONFIG_32BIT
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#ifdef CONFIG_32BIT
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