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MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
Use a new config option to enable R4600 V1 index I-cacheop workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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8c2ede45ed
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802b83627f
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@ -638,6 +638,7 @@ config SGI_IP22
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_BIG_ENDIAN
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select WAR_R4600_V1_INDEX_ICACHEOP
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select MIPS_L1_CACHE_SHIFT_7
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select MIPS_L1_CACHE_SHIFT_7
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help
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help
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This are the SGI Indy, Challenge S and Indigo2, as well as certain
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This are the SGI Indy, Challenge S and Indigo2, as well as certain
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@ -2607,6 +2608,13 @@ config MIPS_ASID_BITS_VARIABLE
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config MIPS_CRC_SUPPORT
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config MIPS_CRC_SUPPORT
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bool
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bool
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# R4600 erratum. Due to the lack of errata information the exact
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# technical details aren't known. I've experimentally found that disabling
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# interrupts during indexed I-cache flushes seems to be sufficient to deal
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# with the issue.
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config WAR_R4600_V1_INDEX_ICACHEOP
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bool
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#
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#
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# - Highmem only makes sense for the 32-bit kernel.
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# - Highmem only makes sense for the 32-bit kernel.
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# - The current highmem code will only work properly on physically indexed
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# - The current highmem code will only work properly on physically indexed
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@ -9,7 +9,6 @@
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#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MACH_GENERIC_WAR_H
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#ifndef __ASM_MACH_GENERIC_WAR_H
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#define __ASM_MACH_GENERIC_WAR_H
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#define __ASM_MACH_GENERIC_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -12,7 +12,6 @@
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* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
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* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
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*/
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*/
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#define R4600_V1_INDEX_ICACHEOP_WAR 1
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#define R4600_V1_HIT_CACHEOP_WAR 1
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#define R4600_V1_HIT_CACHEOP_WAR 1
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#define R4600_V2_HIT_CACHEOP_WAR 1
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#define R4600_V2_HIT_CACHEOP_WAR 1
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_IP27_WAR_H
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#ifndef __ASM_MIPS_MACH_IP27_WAR_H
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#define __ASM_MIPS_MACH_IP27_WAR_H
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#define __ASM_MIPS_MACH_IP27_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_IP28_WAR_H
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#ifndef __ASM_MIPS_MACH_IP28_WAR_H
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#define __ASM_MIPS_MACH_IP28_WAR_H
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#define __ASM_MIPS_MACH_IP28_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -5,7 +5,6 @@
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#ifndef __ASM_MIPS_MACH_IP30_WAR_H
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#ifndef __ASM_MIPS_MACH_IP30_WAR_H
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#define __ASM_MIPS_MACH_IP30_WAR_H
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#define __ASM_MIPS_MACH_IP30_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_IP32_WAR_H
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#ifndef __ASM_MIPS_MACH_IP32_WAR_H
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#define __ASM_MIPS_MACH_IP32_WAR_H
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#define __ASM_MIPS_MACH_IP32_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -12,7 +12,6 @@
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* The RM200C seems to have been shipped only with V2.0 R4600s
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* The RM200C seems to have been shipped only with V2.0 R4600s
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*/
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*/
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 1
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#define R4600_V2_HIT_CACHEOP_WAR 1
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
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#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
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#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
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#define __ASM_MIPS_MACH_TX49XX_WAR_H
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#define __ASM_MIPS_MACH_TX49XX_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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@ -72,16 +72,6 @@
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#define DADDI_WAR 0
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#define DADDI_WAR 0
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#endif
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#endif
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/*
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* Another R4600 erratum. Due to the lack of errata information the exact
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* technical details aren't known. I've experimentally found that disabling
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* interrupts during indexed I-cache flushes seems to be sufficient to deal
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* with the issue.
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*/
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#ifndef R4600_V1_INDEX_ICACHEOP_WAR
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#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
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#endif
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/*
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/*
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* Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
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* Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
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*
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*
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@ -366,7 +366,8 @@ static void r4k_blast_icache_page_indexed_setup(void)
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else if (ic_lsize == 16)
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else if (ic_lsize == 16)
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r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
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r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
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else if (ic_lsize == 32) {
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else if (ic_lsize == 32) {
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if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
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if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
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cpu_is_r4600_v1_x())
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r4k_blast_icache_page_indexed =
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r4k_blast_icache_page_indexed =
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blast_icache32_r4600_v1_page_indexed;
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blast_icache32_r4600_v1_page_indexed;
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else if (TX49XX_ICACHE_INDEX_INV_WAR)
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else if (TX49XX_ICACHE_INDEX_INV_WAR)
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@ -394,7 +395,8 @@ static void r4k_blast_icache_setup(void)
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else if (ic_lsize == 16)
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else if (ic_lsize == 16)
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r4k_blast_icache = blast_icache16;
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r4k_blast_icache = blast_icache16;
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else if (ic_lsize == 32) {
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else if (ic_lsize == 32) {
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if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
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if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
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cpu_is_r4600_v1_x())
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r4k_blast_icache = blast_r4600_v1_icache32;
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r4k_blast_icache = blast_r4600_v1_icache32;
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else if (TX49XX_ICACHE_INDEX_INV_WAR)
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else if (TX49XX_ICACHE_INDEX_INV_WAR)
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r4k_blast_icache = tx49_blast_icache32;
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r4k_blast_icache = tx49_blast_icache32;
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