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clk: mediatek: add infracfg reset controller for mt7988

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Infracfg can also operate as reset controller, add support for it.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240201182409.39878-3-linux@fw-web.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Frank Wunderlich 2024-02-01 19:24:09 +01:00 committed by Stephen Boyd
parent c9d9bea92c
commit 7fcf1ef84f
1 changed files with 23 additions and 0 deletions
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23
drivers/clk/mediatek/clk-mt7988-infracfg.c
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@ -14,6 +14,10 @@
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/reset/mediatek,mt7988-resets.h>
#define MT7988_INFRA_RST0_SET_OFFSET 0x70
#define MT7988_INFRA_RST1_SET_OFFSET 0x80
static DEFINE_SPINLOCK(mt7988_clk_lock);
@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[] = {
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
};
static u16 infra_rst_ofs[] = {
MT7988_INFRA_RST0_SET_OFFSET,
MT7988_INFRA_RST1_SET_OFFSET,
};
static u16 infra_idx_map[] = {
[MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
[MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
};
static struct mtk_clk_rst_desc infra_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_ofs = infra_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
.rst_idx_map = infra_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
};
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.mux_clks = infra_muxes,
.num_mux_clks = ARRAY_SIZE(infra_muxes),
.clk_lock = &mt7988_clk_lock,
.rst_desc = &infra_rst_desc,
};
static const struct of_device_id of_match_clk_mt7988_infracfg[] = {