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https://github.com/torvalds/linux
synced 2024-10-08 12:22:38 +00:00
pinctrl: lynxpoint: Add pin control operations
Add implementation for:
- pin control, group information retrieval: count, name and pins
- pin muxing:
- function information (count, name and groups)
- mux setting
- GPIO control (enable, disable, set direction)
- pin configuration:
- pull disable, up and down
- any other option is treated as not supported.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
Andy Shevchenko
parent
18213ad418
commit
7f32d37009
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@ -146,6 +146,7 @@ static const struct intel_pinctrl_soc_data lptlp_soc_data = {
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/* Bitmapped register offsets */
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#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
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#define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */
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#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
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#define LP_INT_STAT 0x80
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#define LP_INT_ENABLE 0x90
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@ -166,7 +167,10 @@ static const struct intel_pinctrl_soc_data lptlp_soc_data = {
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/* LP_CONFIG2 reg bits */
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#define GPINDIS_BIT BIT(2) /* disable input sensing */
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#define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */
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#define GPIWP_MASK GENMASK(1, 0) /* weak pull options */
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#define GPIWP_NONE 0 /* none */
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#define GPIWP_DOWN 1 /* weak pull down */
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#define GPIWP_UP 2 /* weak pull up */
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/*
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* Lynxpoint gpios are controlled through both bitmapped registers and
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@ -195,6 +199,8 @@ static const struct intel_pinctrl_soc_data lptlp_soc_data = {
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* ...
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* LP94_CONFIG1 (gpio 94) ...
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* LP94_CONFIG2 (gpio 94) ...
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*
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* IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
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*/
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static struct intel_community *lp_get_community(struct intel_pinctrl *lg,
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@ -246,6 +252,308 @@ static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin)
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return !(ioread32(acpi_use) & BIT(pin % 32));
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}
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static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset)
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{
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void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC);
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u32 value;
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value = ioread32(ioxapic_use);
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if (offset >= 8 && offset <= 10)
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return !!(value & BIT(offset - 8 + 0));
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if (offset >= 13 && offset <= 14)
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return !!(value & BIT(offset - 13 + 3));
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if (offset >= 45 && offset <= 55)
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return !!(value & BIT(offset - 45 + 5));
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return false;
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}
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static int lp_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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return lg->soc->ngroups;
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}
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static const char *lp_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int selector)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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return lg->soc->groups[selector].name;
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}
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static int lp_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned int selector,
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const unsigned int **pins,
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unsigned int *num_pins)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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*pins = lg->soc->groups[selector].pins;
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*num_pins = lg->soc->groups[selector].npins;
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return 0;
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}
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static const struct pinctrl_ops lptlp_pinctrl_ops = {
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.get_groups_count = lp_get_groups_count,
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.get_group_name = lp_get_group_name,
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.get_group_pins = lp_get_group_pins,
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};
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static int lp_get_functions_count(struct pinctrl_dev *pctldev)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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return lg->soc->nfunctions;
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}
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static const char *lp_get_function_name(struct pinctrl_dev *pctldev,
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unsigned int selector)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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return lg->soc->functions[selector].name;
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}
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static int lp_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned int selector,
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const char * const **groups,
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unsigned int *num_groups)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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*groups = lg->soc->functions[selector].groups;
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*num_groups = lg->soc->functions[selector].ngroups;
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return 0;
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}
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static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned int function, unsigned int group)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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const struct intel_pingroup *grp = &lg->soc->groups[group];
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unsigned long flags;
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int i;
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raw_spin_lock_irqsave(&lg->lock, flags);
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/* Now enable the mux setting for each pin in the group */
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for (i = 0; i < grp->npins; i++) {
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void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1);
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u32 value;
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value = ioread32(reg);
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value &= ~USE_SEL_MASK;
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if (grp->modes)
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value |= grp->modes[i];
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else
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value |= grp->mode;
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iowrite32(value, reg);
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}
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raw_spin_unlock_irqrestore(&lg->lock, flags);
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return 0;
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}
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static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
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void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
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unsigned long flags;
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u32 value;
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pm_runtime_get(lg->dev);
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raw_spin_lock_irqsave(&lg->lock, flags);
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/*
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* Reconfigure pin to GPIO mode if needed and issue a warning,
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* since we expect firmware to configure it properly.
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*/
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value = ioread32(reg);
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if ((value & USE_SEL_MASK) != USE_SEL_GPIO) {
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iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg);
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dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin);
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}
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/* Enable input sensing */
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iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2);
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raw_spin_unlock_irqrestore(&lg->lock, flags);
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return 0;
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}
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static void lp_gpio_disable_free(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
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unsigned long flags;
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raw_spin_lock_irqsave(&lg->lock, flags);
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/* Disable input sensing */
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iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2);
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raw_spin_unlock_irqrestore(&lg->lock, flags);
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pm_runtime_put(lg->dev);
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}
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static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin, bool input)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
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unsigned long flags;
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u32 value;
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raw_spin_lock_irqsave(&lg->lock, flags);
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value = ioread32(reg);
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value &= ~DIR_BIT;
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if (input) {
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value |= DIR_BIT;
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} else {
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/*
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* Before making any direction modifications, do a check if GPIO
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* is set for direct IRQ. On Lynxpoint, setting GPIO to output
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* does not make sense, so let's at least warn the caller before
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* they shoot themselves in the foot.
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*/
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WARN(lp_gpio_ioxapic_use(&lg->chip, pin),
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"Potential Error: Setting GPIO to output with IOxAPIC redirection");
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}
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iowrite32(value, reg);
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raw_spin_unlock_irqrestore(&lg->lock, flags);
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return 0;
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}
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static const struct pinmux_ops lptlp_pinmux_ops = {
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.get_functions_count = lp_get_functions_count,
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.get_function_name = lp_get_function_name,
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.get_function_groups = lp_get_function_groups,
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.set_mux = lp_pinmux_set_mux,
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.gpio_request_enable = lp_gpio_request_enable,
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.gpio_disable_free = lp_gpio_disable_free,
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.gpio_set_direction = lp_gpio_set_direction,
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};
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static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *config)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
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enum pin_config_param param = pinconf_to_config_param(*config);
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unsigned long flags;
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u32 value, pull;
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u16 arg = 0;
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raw_spin_lock_irqsave(&lg->lock, flags);
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value = ioread32(conf2);
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raw_spin_unlock_irqrestore(&lg->lock, flags);
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pull = value & GPIWP_MASK;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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if (pull)
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return -EINVAL;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (pull != GPIWP_DOWN)
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return -EINVAL;
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arg = 1;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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if (pull != GPIWP_UP)
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return -EINVAL;
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arg = 1;
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break;
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default:
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *configs, unsigned int num_configs)
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{
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
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void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
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enum pin_config_param param;
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unsigned long flags;
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int i, ret = 0;
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u32 value;
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raw_spin_lock_irqsave(&lg->lock, flags);
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value = ioread32(conf2);
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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value &= ~GPIWP_MASK;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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value &= ~GPIWP_MASK;
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value |= GPIWP_DOWN;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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value &= ~GPIWP_MASK;
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value |= GPIWP_UP;
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break;
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default:
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ret = -ENOTSUPP;
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}
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if (ret)
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break;
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}
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if (!ret)
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iowrite32(value, conf2);
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raw_spin_unlock_irqrestore(&lg->lock, flags);
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return ret;
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}
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static const struct pinconf_ops lptlp_pinconf_ops = {
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.is_generic = true,
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.pin_config_get = lp_pin_config_get,
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.pin_config_set = lp_pin_config_set,
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};
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static const struct pinctrl_desc lptlp_pinctrl_desc = {
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.pctlops = &lptlp_pinctrl_ops,
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.pmxops = &lptlp_pinmux_ops,
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.confops = &lptlp_pinconf_ops,
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.owner = THIS_MODULE,
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};
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static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset)
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{
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struct intel_pinctrl *lg = gpiochip_get_data(chip);
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@ -525,6 +833,11 @@ static int lp_gpio_probe(struct platform_device *pdev)
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if (!lg->communities)
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return -ENOMEM;
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lg->pctldesc = lptlp_pinctrl_desc;
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lg->pctldesc.name = dev_name(dev);
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lg->pctldesc.pins = lg->soc->pins;
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lg->pctldesc.npins = lg->soc->npins;
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platform_set_drvdata(pdev, lg);
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io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
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